force
This command allows you to apply stimulus interactively to VHDL signals(not variables), Verilog nets and registers, and SystemC boundary types. It is possible to create a complex sequence of stimuli when the force command is included in a DO file.
Syntax Forcing values, driver type, repetition time or stop time on an object
force {<object_name> <value> [[@]<time_info>][, <value> [@]<time_info>]...
[-deposit | -drive | -drive] [-cancel [@]<time_info>] [-repeat [@]<time_info>]
Arguments
1) <object_name> - specifies the name of the HDL object to be forced.
2) <value>
3) -cancel [@]<time_info> - (optional) cancel the force command at the time specified by <time_info>
4) -drive
- (optional) attach a driver to the object and drives the specified <value> until the object is forced again or until it is unforced
5) -deposit
- (optional) set the object to the specified <value>. The <value> remains until the object is forced again,or it is unforced
6) -freeze
- (optional) freeze the object at the specified <value> until it is forced again or until it is unforced with the noforce command.
- If the -freeze, -drive, or -deposit options are not used, then -freeze is the default for unresolved objects, and -drive is the default for resolved objects.
7) -repeat [@]<time_info> - (optional) repeat a series of forced values and times at the time specified.
8) [@]<time_info>
@
-cancel {520 ns} \\ Relative Time
-cancel {@ 520 ns} \\ Absolute Time
<tim_info> = <time_value> <time_unit>
1 10ns 2 10 ns 3 {10 ns} 4 “10 ns”
