摘要： The following file is to read all design files into syntehsis tool automatically, like Cadence RTL Compiler. 1 set srcbasic ${HDLPATH}/01_V... 阅读全文

摘要： 1 Explicit event The value changes on nets and variable can be used as events to trigger theexecution of a statement. The event can also be based o... 阅读全文

摘要： expr is for Tcl to do math operations. Ittakes all of its arguments ("2 + 2" for example) and evaluates the result as a Tcl "expression". Many comma... 阅读全文

摘要： 1.　0 and 1 (duality: 0 -- 1, ·-- +) X + 0 = X, X·1 = X X + 1 = 1, X ·0 = 02.　Idempotent X + X = X, X ·X = X3.　Involution (X')' = X4.　Complement... 阅读全文

摘要： The status register (SR/R2), used as a source or destination register, can beused in the register mode only addressed with word instructions. The re... 阅读全文

摘要： JC Jump if carry setJHS Jump if higher or sameSyntax JC label JHS labelOperation If C = 1: PC + 2 × offset −> PC If C = 0: exec... 阅读全文

摘要： 3 Skew between signals Skew is the difference in timing between two or more signals, maybe data,clock or both. Clock latency is the total time itta... 阅读全文

摘要： Static Timing Analysis is one of the many techniques available to verify the timing of a digital design. An alternate approach used to verify the ti... 阅读全文

摘要： Write shell script:　1) Editor like vi or mcedi　2) Set execute permission for your script chmod permission your-script-name$ chmod +x your-script... 阅读全文

摘要： 1 Invoke Mdoelsim In order to open Modelsim automatically, it is better to use a shell script to invoke modelsim. 1 #!/bin/bash 2 # --------------... 阅读全文