Q3c:FSM logic

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module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);

    assign Y0 = ((~y[2]&y[0])|(y==3'b100))&~x | (~y[2]&~y[0])&x;
    assign z = (y == 3'b011) | (y == 3'b100);

endmodule