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1 module top_module (
2 input clk,
3 input reset,
4 input [3:1] s,
5 output fr3,
6 output fr2,
7 output fr1,
8 output dfr
9 );
10 parameter A2=3'd0,B1=3'd1,B2=3'd2,C1=3'd3,C2=3'd4,D1=3'd5;
11 reg [2:0] state,next_state;
12
13 always @(*)begin
14 case(state)
15 A2:next_state = s[1]?B1:A2;
16 B1:next_state = s[2]?C1:(s[1]?B1:A2);
17 B2:next_state = s[2]?C1:(s[1]?B2:A2);
18 C1:next_state = s[3]?D1:(s[2]?C1:B2);
19 C2:next_state = s[3]?D1:(s[2]?C2:B2);
20 D1:next_state = s[3]?D1:C2;
21 default:next_state = 'x;
22 endcase
23 end
24
25 always @(posedge clk)begin
26 if(reset)begin
27 state <= A2;
28 end
29 else begin
30 state <= next_state;
31 end
32 end
33
34 always @(*)begin
35 case(state)
36 A2:{fr3,fr2,fr1,dfr} = 4'b1111;
37 B1:{fr3,fr2,fr1,dfr} = 4'b0110;
38 B2:{fr3,fr2,fr1,dfr} = 4'b0111;
39 C1:{fr3,fr2,fr1,dfr} = 4'b0010;
40 C2:{fr3,fr2,fr1,dfr} = 4'b0011;
41 D1:{fr3,fr2,fr1,dfr} = 4'b0000;
42 default:{fr3,fr2,fr1,dfr} = 'x;
43 endcase
44 end
45
46 endmodule
