Design a Moore FSM
1.Decade counter2.Four-bit binary counter3.Decade counter again4.Slow decade counter5.Counter 1-126.Counter 10007.4-digit decimal counter8.12-hour clock9.Hdlbits博文分布10.4-bit shift register11.Left/right rotator12.Left/right arithmetic shift by 1 or 813.5-bit LFSR14.3-bit LFSR15.32-bit LFSR16.Shift register17.Shift register(2)18.3-input LUT19.Rule 9020.Rule 11021.Conway's Game of Life 16x1622.Simple FSM1(asynchronous reset)23.Simple FSM1(synchronous reset)24.Simple FSM2(asynchronous reset)25.Simple FSM2(synchronous reset)26.Simple state transition 327.Simple one-hot state transition 328.Simple FSM 3(asynchronous reset)29.Simple FSM 3(synchronous reset)
30.Design a Moore FSM
31.Lemmings 132.Lemmings 233.Lemmings 334.Lemmings 435.One-hot FSM36.PS/2 packet parser37.PS/2 packet parser and datapath38.Serial receiver39.Serial receiver and datapath40.Serial receiver with parity checking41.Sequence recognition42.Q8:Design a Mealy FSM43.Q5a:Serial two's complementer(Moore FSM)44.Q5b:Serial two's complementer(Moore FSM)45.Q3a:FSM46.Q3b:FSM47.Q3c:FSM logic48.Q6b:FSM next-state logic49.Q6c:FSM next-state logic50.Q6:FSM51.Q2a:FSM52.Q2:One-hot FSM equations53.Q2a: FSM54.Q2b:Another FSM55.Counter with period 100056.4-bit shift register and down counter57.FSM:Sequence 1101 recognizer58.FSM:Enable shift register59.FSM:The complete FSM60.The complete timer61.FSM:One-hot logic equations62.UART 1 module top_module (
2 input clk,
3 input reset,
4 input [3:1] s,
5 output fr3,
6 output fr2,
7 output fr1,
8 output dfr
9 );
10 parameter A2=3'd0,B1=3'd1,B2=3'd2,C1=3'd3,C2=3'd4,D1=3'd5;
11 reg [2:0] state,next_state;
12
13 always @(*)begin
14 case(state)
15 A2:next_state = s[1]?B1:A2;
16 B1:next_state = s[2]?C1:(s[1]?B1:A2);
17 B2:next_state = s[2]?C1:(s[1]?B2:A2);
18 C1:next_state = s[3]?D1:(s[2]?C1:B2);
19 C2:next_state = s[3]?D1:(s[2]?C2:B2);
20 D1:next_state = s[3]?D1:C2;
21 default:next_state = 'x;
22 endcase
23 end
24
25 always @(posedge clk)begin
26 if(reset)begin
27 state <= A2;
28 end
29 else begin
30 state <= next_state;
31 end
32 end
33
34 always @(*)begin
35 case(state)
36 A2:{fr3,fr2,fr1,dfr} = 4'b1111;
37 B1:{fr3,fr2,fr1,dfr} = 4'b0110;
38 B2:{fr3,fr2,fr1,dfr} = 4'b0111;
39 C1:{fr3,fr2,fr1,dfr} = 4'b0010;
40 C2:{fr3,fr2,fr1,dfr} = 4'b0011;
41 D1:{fr3,fr2,fr1,dfr} = 4'b0000;
42 default:{fr3,fr2,fr1,dfr} = 'x;
43 endcase
44 end
45
46 endmodule
合集:
Verilog学习
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