Design a Moore FSM

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-1425.Simple FSM2(synchronous reset)2024-04-1426.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-14

30.Design a Moore FSM2024-04-14

31.Lemmings 12024-04-1432.Lemmings 22024-04-1433.Lemmings 32024-04-1534.Lemmings 42024-04-1535.One-hot FSM2024-04-1536.PS/2 packet parser2024-04-1537.PS/2 packet parser and datapath2024-04-1538.Serial receiver2024-04-1539.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-1645.Q3a:FSM2024-04-1646.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-1660.The complete timer2024-04-1661.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

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 1 module top_module (
 2     input clk,
 3     input reset,
 4     input [3:1] s,
 5     output fr3,
 6     output fr2,
 7     output fr1,
 8     output dfr
 9 ); 
10  parameter A2=3'd0,B1=3'd1,B2=3'd2,C1=3'd3,C2=3'd4,D1=3'd5;
11     reg [2:0] state,next_state;
12     
13     always @(*)begin
14         case(state)
15             A2:next_state = s[1]?B1:A2;
16             B1:next_state = s[2]?C1:(s[1]?B1:A2);
17             B2:next_state = s[2]?C1:(s[1]?B2:A2);
18             C1:next_state = s[3]?D1:(s[2]?C1:B2);
19             C2:next_state = s[3]?D1:(s[2]?C2:B2);
20             D1:next_state = s[3]?D1:C2;
21             default:next_state = 'x;
22         endcase
23     end
24     
25     always @(posedge clk)begin
26         if(reset)begin
27             state <= A2;
28         end
29         else begin
30             state <= next_state;
31         end
32     end
33     
34     always @(*)begin
35         case(state)
36             A2:{fr3,fr2,fr1,dfr} = 4'b1111;
37             B1:{fr3,fr2,fr1,dfr} = 4'b0110;
38             B2:{fr3,fr2,fr1,dfr} = 4'b0111;
39             C1:{fr3,fr2,fr1,dfr} = 4'b0010;
40             C2:{fr3,fr2,fr1,dfr} = 4'b0011;
41             D1:{fr3,fr2,fr1,dfr} = 4'b0000;
42             default:{fr3,fr2,fr1,dfr} = 'x;
43         endcase
44     end
45 
46 endmodule