Simple FSM2(synchronous reset)
1.Decade counter2.Four-bit binary counter3.Decade counter again4.Slow decade counter5.Counter 1-126.Counter 10007.4-digit decimal counter8.12-hour clock9.Hdlbits博文分布10.4-bit shift register11.Left/right rotator12.Left/right arithmetic shift by 1 or 813.5-bit LFSR14.3-bit LFSR15.32-bit LFSR16.Shift register17.Shift register(2)18.3-input LUT19.Rule 9020.Rule 11021.Conway's Game of Life 16x1622.Simple FSM1(asynchronous reset)23.Simple FSM1(synchronous reset)24.Simple FSM2(asynchronous reset)
25.Simple FSM2(synchronous reset)
26.Simple state transition 327.Simple one-hot state transition 328.Simple FSM 3(asynchronous reset)29.Simple FSM 3(synchronous reset)30.Design a Moore FSM31.Lemmings 132.Lemmings 233.Lemmings 334.Lemmings 435.One-hot FSM36.PS/2 packet parser37.PS/2 packet parser and datapath38.Serial receiver39.Serial receiver and datapath40.Serial receiver with parity checking41.Sequence recognition42.Q8:Design a Mealy FSM43.Q5a:Serial two's complementer(Moore FSM)44.Q5b:Serial two's complementer(Moore FSM)45.Q3a:FSM46.Q3b:FSM47.Q3c:FSM logic48.Q6b:FSM next-state logic49.Q6c:FSM next-state logic50.Q6:FSM51.Q2a:FSM52.Q2:One-hot FSM equations53.Q2a: FSM54.Q2b:Another FSM55.Counter with period 100056.4-bit shift register and down counter57.FSM:Sequence 1101 recognizer58.FSM:Enable shift register59.FSM:The complete FSM60.The complete timer61.FSM:One-hot logic equations62.UARTThis is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2, but using synchronous reset.
module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
OFF:begin
next_state=(j)?ON:OFF;
end
ON:begin
next_state=(k)?OFF:ON;
end
endcase
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if(reset)begin
state<=OFF;
end
else begin
state<=next_state;
end
end
// Output logic
// assign out = (state == ...);
assign out=(state==OFF)?0:1;
endmodule
经典三段式写法
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