Simple FSM2(synchronous reset)

合集 - Verilog学习(62)

1.Decade counter2024-04-102.Four-bit binary counter2024-04-103.Decade counter again2024-04-104.Slow decade counter2024-04-105.Counter 1-122024-04-106.Counter 10002024-04-107.4-digit decimal counter2024-04-108.12-hour clock2024-04-109.Hdlbits博文分布2024-04-1010.4-bit shift register2024-04-1111.Left/right rotator2024-04-1112.Left/right arithmetic shift by 1 or 82024-04-1113.5-bit LFSR2024-04-1114.3-bit LFSR2024-04-1115.32-bit LFSR2024-04-1116.Shift register2024-04-1117.Shift register(2)2024-04-1118.3-input LUT2024-04-1119.Rule 902024-04-1220.Rule 1102024-04-1221.Conway's Game of Life 16x162024-04-1222.Simple FSM1(asynchronous reset)2024-04-1423.Simple FSM1(synchronous reset)2024-04-1424.Simple FSM2(asynchronous reset)2024-04-14

25.Simple FSM2(synchronous reset)2024-04-14

26.Simple state transition 32024-04-1427.Simple one-hot state transition 32024-04-1428.Simple FSM 3（asynchronous reset）2024-04-1429.Simple FSM 3（synchronous reset）2024-04-1430.Design a Moore FSM2024-04-1431.Lemmings 12024-04-1432.Lemmings 22024-04-1433.Lemmings 32024-04-1534.Lemmings 42024-04-1535.One-hot FSM2024-04-1536.PS/2 packet parser2024-04-1537.PS/2 packet parser and datapath2024-04-1538.Serial receiver2024-04-1539.Serial receiver and datapath2024-04-1540.Serial receiver with parity checking2024-04-1541.Sequence recognition2024-04-1642.Q8:Design a Mealy FSM2024-04-1643.Q5a:Serial two's complementer(Moore FSM)2024-04-1644.Q5b:Serial two's complementer(Moore FSM)2024-04-1645.Q3a:FSM2024-04-1646.Q3b:FSM2024-04-1647.Q3c:FSM logic2024-04-1648.Q6b:FSM next-state logic2024-04-1649.Q6c:FSM next-state logic2024-04-1650.Q6:FSM2024-04-1651.Q2a：FSM2024-04-1652.Q2:One-hot FSM equations2024-04-1653.Q2a: FSM2024-04-1654.Q2b：Another FSM2024-04-1655.Counter with period 10002024-04-1656.4-bit shift register and down counter2024-04-1657.FSM:Sequence 1101 recognizer2024-04-1658.FSM:Enable shift register2024-04-1659.FSM:The complete FSM2024-04-1660.The complete timer2024-04-1661.FSM:One-hot logic equations2024-04-1662.UART2024-04-16

收起

This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.

This exercise is the same as fsm2, but using synchronous reset.

题目网站

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            OFF:begin
                next_state=(j)?ON:OFF;
            end
            ON:begin
                next_state=(k)?OFF:ON;
            end
        endcase
    end

    always @(posedge clk) begin
        // State flip-flops with synchronous reset
        if(reset)begin
            state<=OFF;
        end
        else begin
            state<=next_state;
        end
    end

    // Output logic
    // assign out = (state == ...);
    assign out=(state==OFF)?0:1;

endmodule

经典三段式写法