Slow decade counter

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

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 1 module top_module (
 2     input clk,
 3     input slowena,
 4     input reset,
 5     output [3:0] q);
 6 always @(posedge clk)begin
 7         if(reset)begin
 8             q<=4'b0;
 9         end
10         else if(slowena)begin
11             if(q==4'd9)begin
12                 q<=4'b0;
13             end
14             else begin
15                 q<=q+1'b1;
16             end
17         end   //等于是一个大嵌套，在大嵌套下再检查一下reset不等于1
18     end
19 
20 endmodule

用slowena控制在当前状态是否要进行递增操作，由图可以看出，当slowena==0，q保持状态不变，当slowena==1，q在下一个周期递增，加1，因为实在下一个周期改变，所以采用时序逻辑