摘要: verdi支持混合查看代码,但是需要提前将代码编译为lib vhdl: vhdlcom -lib libname -2000 -f flist.f -- -lib libname 可不写(默认work.lib++) verilog: vericom -lib libname -sv -f flist 阅读全文
posted @ 2018-07-17 14:30 zxmind 阅读(830) 评论(0) 推荐(0) 编辑
摘要: What is Clock Gating? • Register banks disabled during some clock cycles – Typical implementation uses multiplexers – Clock gating cell replaces multi 阅读全文
posted @ 2018-04-03 09:50 zxmind 阅读(94) 评论(0) 推荐(0) 编辑