RDMA Development Roadmap · corundum/corundum Wiki · GitHub
https://github-wiki-see.page/m/corundum/corundum/wiki/RDMA-Development-Roadmap
RDMA Development Roadmap
Support for RDMA in the form of RoCEv2 in Corundum requires the implementation of many different functionalities, and several of these will require architectural changes to Corundum. Therefore, splitting the development into several phases is necessary to streamline the development process and enable incremental development and integration.
Subsystem pages:
- Subsystem: Ingress and egress pipelines
- Subsystem: RDMA header processing
- Subsystem: RDMA memory management
- Subsystem: RDMA QP state management
- Subsystem: RDMA transport
Phase 1
Phase 1 of the development process includes all of the foundational components upon which RDMA support will be built, including all significant architectural changes.
- Variable-length descriptor support (see RFC: Variable length descriptors)
- Unified DMA address space (including on-card DRAM and/or on-package HBM)
- Shared interface datapath (including support for PFC)
- Application section
- Scheduler section
- Ingress and egress pipeline components (self-contained checksum offload and flow steering)
- Generic PCIe interface/Intel device support
- Segmentation offloading (LSO)
Phase 2
Phase 2 of the development process includes initial support for RoCEv2, storing state in on-FPGA memory. Limiting storage to only on-FPGA SRAM limits scalability, but it simplifies the implementation and keeping things self-contained can be useful for performance reasons (no cache misses if there is no cache) or in embedded applications (limited or no DRAM).
- Queue pair state storage (transport state information)
- Protection domain, memory region, and address translation
- RoCEv2 packet parsing and deparsing
- ICRC computation and verification
- RoCEv2 transport implementation
Phase 3
Phase 3 of the development process includes more scalable implementations of the phase 2 components, storing state in on-host or on-card DRAM and caching state in on-FPGA memory. These changes will enable support for a large number of queues (QPs/CQs/SRQs) as well as more and larger memory regions.
- DRAM-backed caching of queue pair state information
- DRAM-backed caching of memory region information
- DRAM-backed caching of address translation information
【推荐】国内首个AI IDE，深度理解中文开发场景，立即下载体验Trae
【推荐】编程新体验，更懂你的AI，立即体验豆包MarsCode编程助手
【推荐】抖音旗下AI助手豆包，你的智能百科全书，全免费不限次数
【推荐】轻量又高性能的 SSH 工具 IShell：AI 加持，快人一步
· 基于Microsoft.Extensions.AI核心库实现RAG应用
· Linux系列：如何用heaptrack跟踪.NET程序的非托管内存泄露
· 开发者必知的日志记录最佳实践
· SQL Server 2025 AI相关能力初探
· Linux系列：如何用 C#调用 C方法造成内存泄露
· 无需6万激活码！GitHub神秘组织3小时极速复刻Manus，手把手教你使用OpenManus搭建本
· Manus爆火，是硬核还是营销？
· 终于写完轮子一部分：tcp代理 了，记录一下
· 别再用vector＜bool＞了！Google高级工程师：这可能是STL最大的设计失误
· 单元测试从入门到精通
2020-08-21 How to install the NVIDIA drivers on Fedora 32