counter计数器代码

/********************************
Filename:  Counter_en.v
Author  :  ZhangH
Descirpt:  Example of 3-8 counter with enable
Revision:  2011/8/4
Company :  HSEC
********************************/

module counter(clk,out,rst);

parameter WIDTH = 8;
parameter DELAY = 1;

input  clk;
input  rst;
output [WIDTH-1:0] out;

always @(posedge clk or negedge rst)
begin
    if(!rst)
      out = 8'b0;
    else
      out = #DELAY out+1;
end

endmodule