1 //如果是8位的话，只选择低8位传输
2 //因为同步码也是可以自己设置，所以把同步码设置成parameter最好
3 module embeded_2_separate_sync(
4 input clk,
5 input [15:0] din,
6 output[15:0] dout,
7 output h_black_out,//包括同步码在内的Black
8 output v_black_out,//包括同步码在内的Black
9 output h_no_sync_black_out,//不包括同步码在内的Black
10 output h_sync_black_out,//只在4个同步码周期为高电平
11 output de_o,
12 output reg [11:0] line_cnt//计算行数
13
14
15 );
16 parameter VAL_SAV = 8'h80;
17 parameter VAL_EAV = 8'h9d;
18 parameter IVAL_SAV = 8'hab;
19 parameter IVAL_EAV = 8'hb6;
20
21 parameter DATA_WIDTH = 16;
22 reg [DATA_WIDTH-1:0] v_data [6:0] ;
23
24 always @( posedge clk )
25 begin
26 v_data[0] <= din;
27 end
28 genvar i ;
29 generate
30
31 for( i = 0;i <= 5;i = i+1 )
32 begin :data_dly
33 always@( posedge clk )begin
34 v_data[i+1] <= v_data[i];
35 end
36 assign dout = v_data[6];
37
38 end
39 endgenerate
40 wire [6:0] time_ref_code;
41 reg [6:0] time_ref_code_r = 0;
42 assign time_ref_code[6] = (v_data[3][7:0] == 8'hff ) ? 1'b1 : 1'b0;
43 assign time_ref_code[5] = (v_data[2][7:0] == 8'h00 ) ? 1'b1 : 1'b0;
44 assign time_ref_code[4] = (v_data[1][7:0] == 8'h00 ) ? 1'b1 : 1'b0;
45 assign time_ref_code[0] = (v_data[0][7:0] ==VAL_SAV ) ?1'b1 : 1'b0;
46 assign time_ref_code[1] = (v_data[0][7:0] ==VAL_EAV ) ?1'b1 : 1'b0;
47 assign time_ref_code[2] = (v_data[0][7:0] ==IVAL_SAV) ?1'b1 : 1'b0;
48 assign time_ref_code[3] = (v_data[0][7:0] ==IVAL_EAV) ?1'b1 : 1'b0;
49
50
51 always @( posedge clk )
52 begin
53 time_ref_code_r <= time_ref_code;
54 end
55
56 // reg h_sync;
57 // reg v_sync;
58 reg h_sync_r = 0;
59 reg v_sync_r = 0;
60 always @( posedge clk )
61 begin
62 case(time_ref_code_r )
63 7'h71 :begin h_sync_r = 1'b0; v_sync_r = 1'b0; end
64 7'h72 :begin h_sync_r = 1'b1; v_sync_r = 1'b0; end
65 7'h74 :begin h_sync_r = 1'b0; v_sync_r = 1'b1; end
66 7'h78 :begin h_sync_r = 1'b1; v_sync_r = 1'b1; end
67 default : begin h_sync_r = h_sync_r; v_sync_r = v_sync_r; end
68 endcase
69 end
70
71 reg [3:0] h_sync_dly = 0;
72 reg [3:0] v_sync_dly = 0;
73 always @( posedge clk )
74 begin
75 h_sync_dly[3:0] <= {h_sync_dly[2:0],h_sync_r};
76 v_sync_dly[3:0] <= {v_sync_dly[2:0],v_sync_r};
77 end
78
79 reg [1:0] h_sync_r2 = 2'b00;
80 reg [1:0] v_sync_r2 = 2'b00;
81 always @( posedge clk )
82 begin
83 v_sync_r2[1:0] <= {v_sync_r2[0],v_sync_r};
84 h_sync_r2[1:0] <= {h_sync_r2[0],h_sync_r};
85 end
86 wire pos_h = (h_sync_r2 == 2'b01);
87 wire pos_v = (v_sync_r2 == 2'b01);
88 always @( posedge clk )
89 begin
90 if( pos_v )
91 line_cnt <= 0;
92 else if( pos_h )
93 line_cnt <= line_cnt + 1'b1;
94 else
95 line_cnt <= line_cnt;
96 end
97
98 wire h_black ;
99 wire h_no_sync_black;
100 wire h_sync_black;
101 reg h_black_r = 0;
102 reg v_black_r = 0;
103 reg h_no_sync_black_r = 0;
104 reg h_sync_black_r = 0;
105 reg h_sync_orign_r = 0;
106 reg de_r = 0;
107 assign h_black = h_sync_r | h_sync_dly[3] ;
108 assign h_no_sync_black = h_sync_r & h_sync_dly[3] ;
109 assign h_sync_black = h_black^h_no_sync_black ;
110 always @( posedge clk )
111 begin
112 h_black_r <= h_black;
113 de_r <= v_sync_r ? 0 :~h_black;
114 v_black_r <= v_sync_r;
115 h_no_sync_black_r <= h_no_sync_black;
116 h_sync_black_r <= h_sync_black;
117 h_sync_orign_r <= h_sync_r;
118 end
119
120
121
122
123 assign h_black_out = h_black_r;
124 assign v_black_out = v_black_r;
125 assign h_no_sync_black_out = h_no_sync_black_r;
126 assign h_sync_black_out = h_sync_black_r;
127 assign de_o = de_r;
128 endmodule
