linux kernel arm64/mm/proc.S __cpu_setup
cpu setup 正如其名,初始化 CPU 寄存器。
413 无效 TLB transition lookaside buffer 。这相当于是一块 页表的缓存。页表我们刚在 head.S 设置好,使能分页后,应该使用我们 内存中设置的,而不是 TLB 中的,所以 无效 TLB 。
416 ~ 417 CPACR_EL1 寄存器设置,enable FP/ASIMD
418 ~ 419 MDSCR_EL1 寄存器设置, disable access to DCC from el0 .
421 ~ 423 注释内容都很清楚。
428 + 452 设置 mair_el1 寄存器。 相关信息 看 Memory Attribute Indirection Register https://www.cnblogs.com/zhangzhiwei122/p/15975446.html
429 ~ 451 memory tagging extension 功能的支持,相关信息见 https://www.kernel.org/doc/html/latest/arm64/memory-tagging-extension.html 。暂时不知道这个的真实用途
TCR 寄存器准备,相关信息 https://www.cnblogs.com/zhangzhiwei122/p/15972423.html
460 tcr_clear_errata_bits tcr tmp1 tmp2 宏指令在 arch/arm64/include/asm/assembler.h 中,准备 X10 里面的值
462 ~ 470 VA 地址长度,填充到 X10 的 T0SZ 这些bits 位上面。
475 准备 X10 中的IPS bit
476 ~ 487 Enable hardware update of the Access Flags bit Hardware dirty bit management 。 页表项 中 dirty bit 使用硬件管理 ? https://www.cnblogs.com/zhangzhiwei122/p/15975505.html 中AF bit , 略过
488 终于把 x10 寄存器 填入了 TCR_EL1 里面。
492 取 SCTLR_EL1_SET 的值到x0 里面作返回值 ?
404 * __cpu_setup 405 * 406 * Initialise the processor for turning the MMU on. 407 * 408 * Output: 409 * Return in x0 the value of the SCTLR_EL1 register. 410 */ 411 .pushsection ".idmap.text", "awx" 412SYM_FUNC_START(__cpu_setup) 413 tlbi vmalle1 // Invalidate local TLB 414 dsb nsh 415 416 mov x1, #3 << 20 417 msr cpacr_el1, x1 // Enable FP/ASIMD 418 mov x1, #1 << 12 // Reset mdscr_el1 and disable 419 msr mdscr_el1, x1 // access to the DCC from EL0 420 isb // Unmask debug exceptions now, 421 enable_dbg // since this is per-cpu 422 reset_pmuserenr_el0 x1 // Disable PMU access from EL0 423 reset_amuserenr_el0 x1 // Disable AMU access from EL0 424 425 /* 426 * Memory region attributes 427 */ 428 mov_q x5, MAIR_EL1_SET 429#ifdef CONFIG_ARM64_MTE 430 /* 431 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported 432 * (ID_AA64PFR1_EL1[11:8] > 1). 433 */ 434 mrs x10, ID_AA64PFR1_EL1 435 ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4 436 cmp x10, #ID_AA64PFR1_MTE 437 b.lt 1f 438 439 /* Normal Tagged memory type at the corresponding MAIR index */ 440 mov x10, #MAIR_ATTR_NORMAL_TAGGED 441 bfi x5, x10, #(8 * MT_NORMAL_TAGGED), #8 442 443 /* initialize GCR_EL1: all non-zero tags excluded by default */ 444 mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) 445 msr_s SYS_GCR_EL1, x10 446 447 /* clear any pending tag check faults in TFSR*_EL1 */ 448 msr_s SYS_TFSR_EL1, xzr 449 msr_s SYS_TFSRE0_EL1, xzr 4501: 451#endif 452 msr mair_el1, x5 453 /* 454 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for 455 * both user and kernel. 456 */ 457 mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ 458 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ 459 TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS 460 tcr_clear_errata_bits x10, x9, x5 461 462#ifdef CONFIG_ARM64_VA_BITS_52 463 ldr_l x9, vabits_actual 464 sub x9, xzr, x9 465 add x9, x9, #64 466 tcr_set_t1sz x10, x9 467#else 468 ldr_l x9, idmap_t0sz 469#endif 470 tcr_set_t0sz x10, x9 471 472 /* 473 * Set the IPS bits in TCR_EL1. 474 */ 475 tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6 476#ifdef CONFIG_ARM64_HW_AFDBM 477 /* 478 * Enable hardware update of the Access Flags bit. 479 * Hardware dirty bit management is enabled later, 480 * via capabilities. 481 */ 482 mrs x9, ID_AA64MMFR1_EL1 483 and x9, x9, #0xf 484 cbz x9, 1f 485 orr x10, x10, #TCR_HA // hardware Access flag update 4861: 487#endif /* CONFIG_ARM64_HW_AFDBM */ 488 msr tcr_el1, x10 489 /* 490 * Prepare SCTLR 491 */ 492 mov_q x0, SCTLR_EL1_SET 493 ret // return to head.S 494SYM_FUNC_END(__cpu_setup) 495