arm-a53-configuration signals
翻译 https://developer.arm.com/documentation/ddi0500/j/Signal-Descriptions/Configuration-signals?lang=en
Table A.3 shows the configuration signals.
Signal | Direction | Description |
---|---|---|
AA64nAA32[CN:0] | Input |
Register width state:
This pin is sampled only during reset of the processor. |
CFGEND[CN:0] | Input |
Endianness configuration at reset. It sets the initial value of the EE bits in the CP15 SCTLR_EL3 and SCTR_S registers:
This pin is sampled only during reset of the processor. |
CFGTE[CN:0] | Input |
Enable T32 exceptions. It sets the initial value of the TE bit in the CP15 SCTLR register:
This pin is sampled only during reset of the processor. |
CLUSTERIDAFF1[7:0] | Input |
Value read in the Cluster ID Affinity Level 1 field, MPIDR bits[15:8], of the CP15 MPIDR register. These pins are sampled only during reset of the processor. |
CLUSTERIDAFF2[7:0] | Input |
Value read in the Cluster ID Affinity Level 2 field, MPIDR bits[23:16], of the CP15 MPIDR register. These pins are sampled only during reset of the processor. |
CP15SDISABLE[CN:0] | Input |
Disable write access to some secure CP15 registers. |
CRYPTODISABLE[CN:0] | Input |
Disables the Cryptography Extensions. This pin is sampled only during reset of the processor. |
RVBARADDRx[39:2] | Input |
Reset Vector Base Address for executing in 64-bit state. These pins are sampled only during reset of the processor. |
VINITHI[CN:0] | Input |
Location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 SCTLR register:
This pin is sampled only during reset of the processor. |