随笔档案 (761)

(duckdb_book) frank@ZZHUBT:~$ python
Python 3.13.1 (main, Jan 15 2025, 18:12:47) [GCC 11.4.0] on linux
Type "help", "copyright", "credits" or "license" for more information.
>>> import polars as pl
/home/frank/venvs/duckdb_book/lib/python3.13/site-packages/polars/_cpu_check.py:258: RuntimeWarning: Missing required CPU features.

The following required CPU features were not detected:
    avx, avx2, fma
Continuing to use this version of Polars on this processor will likely result in a crash.
Install the `polars-lts-cpu` package instead of `polars` to run Polars with better compatibility.

Hint: If you are on an Apple ARM machine (e.g. M1) this is likely due to running Python under Rosetta.
It is recommended to install a native version of Python that does not run under Rosetta x86-64 emulation.

If you believe this warning to be a false positive, you can set the `POLARS_SKIP_CPU_CHECK` environment variable to bypass this check.

  warnings.warn(
Illegal instruction (core dumped)

How to Check Support for AVX/AVX2/FMA:

Linux: You can run the following command to check if your CPU supports these features:

lscpu

Look for the flags avx, avx2, and fma in the output. If they’re not present, your CPU doesn’t support them.
macOS: Use the following command:

sysctl -a | grep machdep.cpu.features

If AVX or FMA is listed, your CPU supports those features.
Windows: You can check the CPU information with the following command in Command Prompt:

wmic cpu get caption, deviceid, name, numberofcores, maxclockspeed, status

The virtualized CPU doesn't support AVX/AVX2/FMA:

(duckdb_book) frank@ZZHUBT:~$ lscpu
Architecture:             x86_64
  CPU op-mode(s):         32-bit, 64-bit
  Address sizes:          39 bits physical, 48 bits virtual
  Byte Order:             Little Endian
CPU(s):                   2
  On-line CPU(s) list:    0,1
Vendor ID:                GenuineIntel
  Model name:             13th Gen Intel(R) Core(TM) i5-1340P
    CPU family:           6
    Model:                186
    Thread(s) per core:   1
    Core(s) per socket:   2
    Socket(s):            1
    Stepping:             2
    BogoMIPS:             4377.60
    Flags:                fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx rdtscp lm constant_tsc rep_good nopl x
                          topology nonstop_tsc cpuid tsc_known_freq pni pclmulqdq ssse3 cx16 pcid sse4_1 sse4_2 movbe popcnt aes rdrand hypervisor lahf_lm abm 3dnowprefetch ibr
                          s_enhanced fsgsbase bmi1 bmi2 invpcid rdseed adx clflushopt sha_ni arat md_clear flush_l1d arch_capabilities
Virtualization features:  
  Hypervisor vendor:      KVM
  Virtualization type:    full
Caches (sum of all):      
  L1d:                    96 KiB (2 instances)
  L1i:                    64 KiB (2 instances)
  L2:                     2.5 MiB (2 instances)
  L3:                     24 MiB (2 instances)
NUMA:                     
  NUMA node(s):           1
  NUMA node0 CPU(s):      0,1
Vulnerabilities:          
  Gather data sampling:   Not affected
  Itlb multihit:          Not affected
  L1tf:                   Not affected
  Mds:                    Not affected
  Meltdown:               Not affected
  Mmio stale data:        Not affected
  Reg file data sampling: Mitigation; Clear Register File
  Retbleed:               Mitigation; Enhanced IBRS
  Spec rstack overflow:   Not affected
  Spec store bypass:      Vulnerable
  Spectre v1:             Mitigation; usercopy/swapgs barriers and __user pointer sanitization
  Spectre v2:             Mitigation; Enhanced / Automatic IBRS; RSB filling; PBRSB-eIBRS SW sequence; BHI SW loop, KVM SW loop
  Srbds:                  Not affected
  Tsx async abort:        Not affected

PS C:\Users\ZhangZhihui> wmic cpu get caption, deviceid, name, numberofcores, maxclockspeed, status
wmic : 无法将“wmic”项识别为 cmdlet、函数、脚本文件或可运行程序的名称。请检查名称的拼写，如果包括路径，请确保路径正确，然后再试一次。
所在位置 行:1 字符: 1
+ wmic cpu get caption, deviceid, name, numberofcores, maxclockspeed, s ...
+ ~~~~
    + CategoryInfo          : ObjectNotFound: (wmic:String) [], CommandNotFoundException
    + FullyQualifiedErrorId : CommandNotFoundException

Starting with Windows 11, the wmic command has been deprecated and removed in favor of PowerShell commands and other modern tools.

Using Coreinfo (Recommended for CPU Feature Detection):

Coreinfo is a small utility from Sysinternals that can show you detailed CPU capabilities, including AVX, AVX2, and FMA.

Steps to use Coreinfo:

Download Coreinfo:
- Go to the Coreinfo download page and download the zip file.
Extract and Run Coreinfo:
- Extract the contents of the zip file.
- Open PowerShell or Command Prompt as Administrator.
- Navigate to the directory where you extracted Coreinfo.exe.
- Run the command:
  
  powershell
  
  .\coreinfo.exe
Check the output for the features:
- You’ll see output like:
  
  AVX * Supports AVX AVX2 * Supports AVX2 FMA * Supports FMA
This will tell you if your CPU supports AVX, AVX2, and FMA instructions.

It turns out my physical CPU supports AVX, AVX2 and FMA:

PS E:\software\Coreinfo> .\Coreinfo.exe

Coreinfo v3.6 - Dump information on system CPU and memory topology
Copyright (C) 2008-2022 Mark Russinovich
Sysinternals - www.sysinternals.com


13th Gen Intel(R) Core(TM) i5-1340P
Intel64 Family 6 Model 186 Stepping 2, GenuineIntel
Microcode signature: 00004122
HTT             *       Hyperthreading enabled
CET             *       Supports Control Flow Enforcement Technology
Kernel CET      -       Kernel-mode CET Enabled
User CET        *       User-mode CET Allowed
HYPERVISOR      *       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            *       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              *       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          -       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           -       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX instruction extensions
AVX2            *       Supports AVX2 instruction extensions
AVX-512-F       -       Supports AVX-512 Foundation instructions
AVX-512-DQ      -       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   -       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      -       Supports AVX-512 conflict detection instructions
AVX-512-BW      -       Supports AVX-512 byte and word instructions
AVX-512-VL      -       Supports AVX-512 vector length instructions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          *       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             *       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           *       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            *       Supports PCIDs and settable CR4.PCIDE
INVPCID         *       Supports INVPCID instruction
PDCM            *       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    *       Local APIC supports one-shot deadline timer
TSC-INVARIANT   *       TSC runs at constant rate
xTPR            *       Supports disabling task priority messages

EIST            *       Supports Enhanced Intel Speedstep
ACPI            *       Implements MSR for power management
TM              *       Implements thermal monitor circuitry
TM2             *       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          *       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             *       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 00000020 (Basic), 80000008 (Extended).
Maximum implemented address width: 48 bits (virtual), 39 bits (physical).

Processor signature: 000B06A2

Logical to Physical Processor Map:
**--------------  Physical Processor 0 (Hyperthreaded)
--**------------  Physical Processor 1 (Hyperthreaded)
----**----------  Physical Processor 2 (Hyperthreaded)
------**--------  Physical Processor 3 (Hyperthreaded)
--------*-------  Physical Processor 4
---------*------  Physical Processor 5
----------*-----  Physical Processor 6
-----------*----  Physical Processor 7
------------*---  Physical Processor 8
-------------*--  Physical Processor 9
--------------*-  Physical Processor 10
---------------*  Physical Processor 11

Logical Processor to Socket Map:
****************  Socket 0

Logical Processor to NUMA Node Map:
****************  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
**--------------  Data Cache          0, Level 1,   48 KB, Assoc  12, LineSize  64
**--------------  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
**--------------  Unified Cache       0, Level 2,    1 MB, Assoc  10, LineSize  64
****************  Unified Cache       1, Level 3,   12 MB, Assoc   8, LineSize  64
--**------------  Data Cache          1, Level 1,   48 KB, Assoc  12, LineSize  64
--**------------  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
--**------------  Unified Cache       2, Level 2,    1 MB, Assoc  10, LineSize  64
----**----------  Data Cache          2, Level 1,   48 KB, Assoc  12, LineSize  64
----**----------  Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
----**----------  Unified Cache       3, Level 2,    1 MB, Assoc  10, LineSize  64
------**--------  Data Cache          3, Level 1,   48 KB, Assoc  12, LineSize  64
------**--------  Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
------**--------  Unified Cache       4, Level 2,    1 MB, Assoc  10, LineSize  64
--------*-------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------*-------  Instruction Cache   4, Level 1,   64 KB, Assoc   8, LineSize  64
--------****----  Unified Cache       5, Level 2,    2 MB, Assoc  16, LineSize  64
---------*------  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
---------*------  Instruction Cache   5, Level 1,   64 KB, Assoc   8, LineSize  64
----------*-----  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
----------*-----  Instruction Cache   6, Level 1,   64 KB, Assoc   8, LineSize  64
-----------*----  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
-----------*----  Instruction Cache   7, Level 1,   64 KB, Assoc   8, LineSize  64
------------*---  Data Cache          8, Level 1,   32 KB, Assoc   8, LineSize  64
------------*---  Instruction Cache   8, Level 1,   64 KB, Assoc   8, LineSize  64
------------****  Unified Cache       6, Level 2,    2 MB, Assoc  16, LineSize  64
-------------*--  Data Cache          9, Level 1,   32 KB, Assoc   8, LineSize  64
-------------*--  Instruction Cache   9, Level 1,   64 KB, Assoc   8, LineSize  64
--------------*-  Data Cache         10, Level 1,   32 KB, Assoc   8, LineSize  64
--------------*-  Instruction Cache  10, Level 1,   64 KB, Assoc   8, LineSize  64
---------------*  Data Cache         11, Level 1,   32 KB, Assoc   8, LineSize  64
---------------*  Instruction Cache  11, Level 1,   64 KB, Assoc   8, LineSize  64

Logical Processor to Group Map:
****************  Group 0

Have to install polars-lts-cpu instead of polars:

(duckdb_book) frank@ZZHUBT:~$ pip uninstall polars
Found existing installation: polars 1.19.0
Uninstalling polars-1.19.0:
  Would remove:
    /home/frank/venvs/duckdb_book/lib/python3.13/site-packages/polars-1.19.0.dist-info/*
    /home/frank/venvs/duckdb_book/lib/python3.13/site-packages/polars/*
Proceed (Y/n)? Y
  Successfully uninstalled polars-1.19.0

(duckdb_book) frank@ZZHUBT:~$ pip install polars-lts-cpu
Collecting polars-lts-cpu
  Downloading polars_lts_cpu-1.19.0-cp39-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl.metadata (14 kB)
Downloading polars_lts_cpu-1.19.0-cp39-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl (32.4 MB)
   ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ 32.4/32.4 MB 1.6 MB/s eta 0:00:00
Installing collected packages: polars-lts-cpu
Successfully installed polars-lts-cpu-1.19.0