Safe or Glitch-Free Clock Gating
摘要：
Following is an example of a way to perform glitch-free clock gating. The clock is stalled in the high state one clock cycle after gate is asserted high. It is safe as long as the delay through the re... 阅读全文
posted @ 2010-10-11 22:03 Homography Matrix 阅读(1170) 评论(0) 推荐(1) 编辑
