Safe or Glitch-Free Clock Gating

 

Following is an example of a way to perform glitch-free clock gating. The clock is stalled in the high state one clock cycle after gate is asserted high. It is safe as long as the delay through the register is less than a half clock cycle.

 

 

典型的clock gating cell， 可以避免ENL中glith的产生。
当ck为低电平时,EN可以通过latch,latch 的输出端信号和EN一致,此时由于ck为低,ENL=0
当ck由低变高时,latch锁死,latch 的输出为EN最后的值,c k为高,与门的输出为EN.当然此时EN一定为高.
所以形成脉冲.

 Low pass latch + AND can gate the rising edge triggered FF. This will make the enable pin has 1T delay. When use Low pass latch + AND, if you pass STA, there will be no glitch. OR gate can also gate the rising edge triggered FF, if you pass STA, there will be also no glitch.
ps: when use write your own gate module, you'd bettern instance the cell library cell directly, this will disable synthesis tool do optimization on your gate logic. and there may have clock gating cells in your cell library now, may named as ICG cell.