STA fundamental

STA fundamental

a). Timing paths

Timing path Startpoints

- Input ports,

- Clock pins of flip-flops

Timing path Endpoints

- Output ports,

- all input pins of flip-flops except clock pins

 

Note: In STA, Setup is checked at next edge and hold is checked at same edge

 

 

 

b).Setup time: the time required for the data to be stable before the clock edge

CALCULATION:

Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max)

Required time = clock adjust + clock delay FF2 (min) - set up time FF2

Slack = Required time - Arrival time (since we want data to arrive before it is required)

clock adjust = clock period (since setup is analyzed at next edge)

Note: setup violations occur when Gate Delays are Big .Hence use max (Delay) Corner.

 

c).Hold time: the time required for the data to remain stable after the clock edge

CALCULATION:

Arrival time (min) = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min)

Required time = clock adjust + clock delay FF2 (max) + hold time FF2

Slack = Arrival time - Required time (since we want data to arrive after it is required)

clock adjust = 0 (since hold is analyzed at same edge)

 

An internal hold violation occurs when a receiving clock is presented with data that has not met the hold requirement. This condition usually occurs because of clock skew introduced by gated clocks in the design.

Note: Hold Violations occur when Gate Delays are small. Hence use Min (Delay) Corner.

 

d).Slew or Transition time:

Time taken for a signal to reach from 10% of VDD to 90% VDD

 

e).Jitter

- Variation in period from clock source (PLL)

 

f).Insertion Delay

- delay from clock source to the clock endpoint

 

g).Skew

- Difference in arrival time at clock endpoints

 

h).Clock skew         

-clock skew = clock insertion delay of FF1 - clock insertion delay of FF2

The difference in the arrival time of a clock signal at two different registers, which can be caused by path length differences between two clock paths, or by using gated or rippled clocks. Clock skew is the most common cause of internal hold violations.

I). Clock network delay

-Clock network delay = Clock source latency + Clock network latency.

 

J).Pre vs Post Clock Tree Synthesis (CTS)

K).False path

- any logically false path

- any register to register path which you do not wish to constrain

- these paths are excluded from timing analysis

L) Multi cycle path

for setup: clock adjust time greater then one clock period

for hold: clock adjust greater then zero time

 

M) Recovery time

-Recovery time is the minimum time that an asynchronous control must be stable before the clock active-edge transition.

 

N) Removal time

-Removal time is the minimum length of time that an asynchronous control must be stable after the clock active-edge transition.