Troubleshooting Internal Hold Violations

Troubleshooting Internal Hold Violations

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The Classic Timing Analyzer reports internal hold violations in the Clock Hold report. The Classic Timing Analyzer assumes the most stringent hold relationship possible in detecting internal hold violations in a design by verifying that data feeding a register is stable at the register's input for the required length of time, after the clock signal is asserted at the clock pin, in order to properly latch the data. However, since the Classic Timing Analyzer does not automatically infer the proper relationship between absolute clocks (not dependent on other clocks) and derived clocks (dependent on other clocks) in the design, you must first define the performance requirements and relationships of all clocks in your design by specifying clock settings before the Classic Timing Analyzer can accurately analyze multiclock designs. The following image shows the default set-up and hold relationship for a simple transfer within the same global clock domain.

Example of Default Set-up and Hold Relationship

 

Important: All hold timing violations detected in HardCopy designs will be corrected by Altera during the HardCopy conversion or implementation process.

 

Cause of Internal Hold Violations

An internal hold violation occurs when a receiving clock is presented with data that has not met the hold requirement. This condition usually occurs because of clock skew introduced by gated clocks in the design. The example above is unlikely to produce an internal hold violation because the global clock network is designed to reduce clock skew. Therefore, the data path would have to be less than zero in order to cause a hold violation. However, gated clocks may add delay to the destination clock path, producing clock skew that can lead to internal hold violations.

Example of Internal Hold Violations

 

Correcting Internal Hold Violations

Use one or more of the following guidelines to correct detected internal hold violations:

 

Remove gated clocks and use a clock enable:

This guideline is the preferred method of eliminating clock skew and hold violations; however, it may not always be possible. Replacing gated clocks with clock enables eliminates clock skew by ensuring that all clocks are on the main clock tree. When converting from a gated clock to a clock enable, it is important to note that a gated clock is edge-sensitive, while a clock enable is level-sensitive. Therefore, a clock enable should only be active for one cycle before the gated clock's edge, and it should be active for only one clock cycle per gated clock's rising edge. In order for the clock enable to emulate the desired behavior of the gated clock, a single pulse must be generated once per clock cycle before the gated clock is asserted, as shown in the following image.

Example of Single Pulse Generation Before Gate Clock is Asserted

Constrain the hold violation path:

Assigning the Multicycle Hold assignment to the hold violation path is effective when the Quartus II software's hold requirement is too stringent. For example, in a design in which data is passed from one clock domain to another, and the source maintains the same data for multiple clock cycles before it is clocked into the destination register, assigning a Multicycle Hold or Source Multicycle Hold allows you to relax the hold requirement for the path.

Reduce clock skew:

You may be able to reduce the clock skew by speeding up the clock signal. Reducing the clock skew may be effective in correcting hold violations in which a derived clock with low fan-out is propagated onto a global channel. It is important to note that although global clock trees are designed for low skew, they are not necessarily the fastest device resource. Therefore, setting the Global Signal logic option to Off for the gated clock may speed up the signal by assigning it to a faster non-global channel. Alternatively, you may be able to create LogicLock regions or create custom regions to group all the gated clock registers close to the gated clock source. However, this may have the unintended effect of reducing the data delay, thereby eliminating the benefit.

Increase data delay:

You may be able to increase the data delay until it exceeds the clock skew, thus eliminating the hold violation. You can increase the data delay by increasing the levels of logic in the path and/or increasing the routing delays. You can increase the levels of logic by assigning the Logic Cell Insertion logic option. In addition, you can create LogicLock regions or create custom regions to disperse the logic throughout the device, thereby increasing the physical distances and routing delays between the gated clock registers. However, if the gated clock is not on a dedicated global signal, this may have the unintended effect of increasing the clock skew, thereby eliminating the benefit.