How2 fix setup and hold violation?

http://www.edaboard.com/thread84656.html

Setup time fixing:
1) reducing combinational logic delay by minimising number of logic levels
2) splitting the combinational logic
3) Implimenting Pipelining
4) Using double syncronizer using flipflops

Hold time fixing:
1) Can be fixed by adding delays on input ports
2) adjusting clock speed

Generally hold time is not in the user control

setup violations occur when Gate Delays are Big .Hence use max (Delay) Corner.
Hold Violations occur when Gate Delays are Small. Hence use Min (Delay) Corner.

If there both exsit setup and hold violation, you need to fix up hold violation issue firstly.

setup time violations can be taken care of by reducing the clock frequency. but the hold time violation is due to unnecessary delays on the clock tree.(unwanted clock skew due to bad clock tree design or place and route).therefore removing the hold time violation is a preferred option. this might as well require some changes in the design netlist, or insert buffers in P&R stage if slack is not big.