pulse ack_req

 1 module pulse_ack_req(rst_n, clkA, clkB, flag_in, flag_out, ack);
 2     input rst_n;
 3     input clkA;
 4     input clkB;
 5     input flag_in;
 6     output flag_out;
 7     // for test
 8     output ack;
 9     wire ack;
10     reg flag_toggle;
11     
12     reg[2:0] synA2B_flag; 
13     reg[2:0] synB2A_flag;
14     
15     //toggle circuit
16     always@(posedge flag_in or negedge rst_n)
17        if(!rst_n)
18           flag_toggle <= 1'b0;
19        else if(!ack)
20           flag_toggle <= ~ flag_toggle;
21     
22     //synchronization circuit
23     always@(posedge clkB or negedge rst_n)
24        if(!rst_n)
25           synA2B_flag <= 3'b0;
26        else
27           synA2B_flag <= {synA2B_flag[1:0], flag_toggle};
28  
29     //level change detector
30        assign flag_out = synA2B_flag[2] ^ synA2B_flag[1];
31     
32     //ack generation circuit
33        always@(posedge clkA or negedge rst_n)
34           if(!rst_n)
35              synB2A_flag <= 3'b0;
36           else
37              synB2A_flag <= {synB2A_flag[1:0], synA2B_flag[2]};
38           
39        assign ack = synB2A_flag[2] ^ synB2A_flag[1];
40        
41        
42    endmodule
43 

pulse ack_req