one tip for HDL coding
In previos work, when I encounter the situation counter reach full state (such as counter[3:0] reaches 4'b1111), I used to manually flip counter to zeros on next rsing clock edge . However, I have ignored the fact that counter will automatically overflow on next rising clock edge when it reaches full state.
Codes below are part of synchronous FIFO design, I will release the rest when I finish testing.
Previous coding style
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begin
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if(wr_addr != 4'b1111)
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begin
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if(rd_addr != wr_addr + 4'b0001)
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ns = wcntstate;
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else
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ns = fullstate;
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end
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else
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begin
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if(rd_addr != 4'b0000)
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ns = wcntstate;
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else
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ns = fullstate;
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end
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end
![](https://www.cnblogs.com/Images/OutliningIndicators/None.gif)
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![](https://www.cnblogs.com/Images/OutliningIndicators/None.gif)
modified coding style
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begin
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if(wr_addr != rd_addr + 4'b0001)
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ns = wcntstate;
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else
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ns = emptystate;
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end
![](https://www.cnblogs.com/Images/OutliningIndicators/None.gif)
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posted on 2009-10-23 17:20 Homography Matrix 阅读(330) 评论(0) 编辑 收藏 举报