altshift_taps
Description: Output from the regularly spaced taps along the shift register.
Comment: Output port WIDTH *NUMBER_OF_TAPS wide. This port is an aggregate of all the regularly spaced taps (each WIDTH bits) along the shift register
You can determine the width of the 'shiftin' input bus and the 'shiftout'
output bus, set the number of taps, create groups for each tap output, and
set the width of the distance between the taps. The minimum width is 3
bits. You can also create a clock enable, if applicable to your design and
select the type of memory block to use, M512 or M4K. Cyclone II and
Cyclone devices are used in M4K memory blocks only.
Comment: Output port WIDTH *NUMBER_OF_TAPS wide. This port is an aggregate of all the regularly spaced taps (each WIDTH bits) along the shift register
You can determine the width of the 'shiftin' input bus and the 'shiftout'
output bus, set the number of taps, create groups for each tap output, and
set the width of the distance between the taps. The minimum width is 3
bits. You can also create a clock enable, if applicable to your design and
select the type of memory block to use, M512 or M4K. Cyclone II and
Cyclone devices are used in M4K memory blocks only.
posted on 2009-10-09 16:43 Homography Matrix 阅读(1810) 评论(0) 编辑 收藏 举报
