官方文档说明
intel x64开发人员手册之Effects of a LOCK Operation on Internal Processor Caches章节有明确说明
8.1.4 Effects of a LOCK Operation on Internal Processor Caches
For the Intel486 and Pentium processors, the LOCK# signal is always asserted on the bus during a LOCK operation,
even if the area of memory being locked is cached in the processor.
For the P6 and more recent processor families, if the area of memory being locked during a LOCK operation is
cached in the processor that is performing the LOCK operation as write-back memory and is completely contained
in a cache line, the processor may not assert the LOCK# signal on the bus. Instead, it will modify the memory location internally and allow it’s cache coherency mechanism to ensure that the operation is carried out atomically. This
operation is called “cache locking.” The cache coherency mechanism automatically prevents two or more processors that have cached the same area of memory from simultaneously modifying data in that area.
主要意思就是：
对于internal的Intel486和Pentium处理器，LOCK#信号总是在总线上进行断言，即使被锁定的内存区域被缓存在处理器中。这个操作称为“总线锁定”；
对于P6和最近的处理器系列，如果要操作的内存区域已经被缓存在处理器中，若此发生回写内存操作，LOCK#信号不能总是在总线上进行断言。相反，允许它的缓存一致性机制生效，以确保操作是原子进行的。 这 操作称为“缓存锁定”。 缓存一致性机制自动防止两个或多个缓存了相同内存区域的处理器同时修改该区域的数据。
也就是说，在P6之前，不包括P6的cpu，Lock指令是总线锁，P6之后的cpu优先缓存锁，其次总线锁。
