加法器
1. 半加器
1 module HalfAdder(a,b,So,Co);
2
3 input a,b;
4 output reg So,Co;
5
6 always@(a or b)
7 begin
8 case({a,b})
9 2'b00:
10 begin
11 So=0;
12 Co=0;
13 end
14 2'b01:
15 begin
16 So=1;
17 Co=0;
18 end
19 2'b10:
20 begin
21 So=1;
22 Co=0;
23 end
24 2'b11:
25 begin
26 So=0;
27 Co=1;
28 end
29 endcase
30 end
31
32 endmodule
33
2. 全加器
1 module fulladder(a,b,cin,sum,cout);
2
3 input a,b,cin;
4 output sum,cout;
5
6 always @(*)//@(*)代表所有的输入变量，等价于always @(a,b,cin)
7 begin
8 {cout,sum}=a+b+cin;
9 end
10
11 endmodule
4. 8位全加器
1 module full8bitadder(sum,cout,a,b,cin);
2
3 input [7:0] a,b;
4 input cin;
5 output [7:0]sum;
6 output cout;
7 assign{cout,sum}=a+b+cin;
8
9 endmodule
5. 流水线加法器
流水线设计技术基本思想是在逻辑电路中加入若干寄存器来暂存中间结果，多用了寄存器资源，但减小了每一级组合电路的时延，因此提高了整个加法器的运行频率。
1 module PipelineAdder(cout,sum,a,b,cin,clk);
2
3 input [7:0] a,b;
4 input cin,clk;
5 output reg[7:0] sum;
6 output sum;
7
8 reg[3:0] tempa,tempb,firsts;
9 reg firstc;
10
11 always @(posedge clk)
12 begin
13 {firstc,firsts}=a[3:0]+b[3:0]+cin;
14 tempa=a[7:4];tempb=b[7:4];
15 end
16
17 always @(posedge clk)
18 begin
19 {cout,sum[7:4]}=tempa+tempb+firstc;
20 sum[3:0]=firsts;
21 end
22 endmodule
2
3 input [7:0] a,b;
4 input cin,clk;
5 output reg[7:0] sum;
6 output sum;
7
8 reg[3:0] tempa,tempb,firsts;
9 reg firstc;
10
11 always @(posedge clk)
12 begin
13 {firstc,firsts}=a[3:0]+b[3:0]+cin;
14 tempa=a[7:4];tempb=b[7:4];
15 end
16
17 always @(posedge clk)
18 begin
19 {cout,sum[7:4]}=tempa+tempb+firstc;
20 sum[3:0]=firsts;
21 end
22 endmodule
