Verilog HDL 任意整数分频

//任意整数倍的分频器
module CLK_Division(CLK_In,CLK_In_N,CLK_Out);
       input CLK_In;
       input [31:0] CLK_In_N;
       output CLK_Out;
       reg CLK_Out;

       reg [31:0] CLK_Count;
       reg [31:0] CLK_Count_H; //分频计数器高电平计数
       reg [31:0] CLK_Count_L; //分频计数器低电平计数
       reg CLK_Count_Odd; //分频计数器奇数分频时低电平计数校正
       reg CLK_Div_1;
       reg CLK_Div_2;

     always
     begin
         if(CLK_In_N==0)CLK_Out<=0;
         else if(CLK_In_N==1)CLK_Out<=CLK_In;
         else CLK_Out<=CLK_Div_1|CLK_Div_2;
         CLK_Count_H<=CLK_In_N/2;
         CLK_Count_Odd<=CLK_In_N[0];
         CLK_Count_L<=CLK_Count_H+CLK_Count_Odd; //分频计数器奇数分频时低电平计数校正
     end

     always @ (posedge CLK_In)
     begin
         if((CLK_Div_1==1)&&(CLK_Count>=CLK_Count_H))
         begin
              CLK_Count<=1;
              CLK_Div_1<=0;
         end
         else if(CLK_Count>=CLK_Count_L)
   begin
             CLK_Count<=1;
             CLK_Div_1<=1;
         end
         else CLK_Count<=CLK_Count+1;
     end

    always @ (negedge CLK_In)
    begin
         if((CLK_Div_1==1)&&(CLK_Count_Odd==1))CLK_Div_2<=1;
         else CLK_Div_2<=0;
    end

endmodule