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//*******************************************************//
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// 任意整数分频模块 //
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//*******************************************************//
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//功能:对输入时钟clock进行F_DIV倍分频后输出clk_out。
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//其中F_DIV为分频系数,分频系数范围为1~2^n (n=F_DIV_WIDTH)
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//若要改变分频系数,改变参数F_DIV或F_DIV_WIDTH到相应范围即可。
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//若分频系数为偶数,则输出时钟占空比为50%;
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//若分频系数为奇数,则输出时钟占空比取决于输入时钟占空比和分
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//频系数(当输入为50%时,输出也是50%)。
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//--------------------------------------------------------
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//奇数倍分频:三倍分频的时序图如下所示。
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// 1 2 3 4 5 6
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//clock |--|__|--|__|--|__|--|__|--|__|--|__|
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//clk_p_r |_____|-----------|_____|-----------|
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//clk_n_r ---|_____|-----------|_____|---------
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//clk_out |________|--------|________|--------|
17![](/Images/OutliningIndicators/None.gif)
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module int_div(clock,clk_out);
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//I/O口声明
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input clock; //输入时钟
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output clk_out; //输出时钟
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//内部寄存器
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reg clk_p_r; //上升沿输出时钟
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reg clk_n_r; //下降沿输出时钟
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reg[F_DIV_WIDTH - 1:0] count_p; //上升沿脉冲计数器
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reg[F_DIV_WIDTH - 1:0] count_n; //下降沿脉冲计数器
29![](/Images/OutliningIndicators/None.gif)
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//参数--分频系数
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parameter F_DIV = 48000000; //分频系数<<<<-----修改这里
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parameter F_DIV_WIDTH = 32; //分频计数器宽度
33![](/Images/OutliningIndicators/None.gif)
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wire full_div_p; //上升沿计数满标志
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wire half_div_p; //上升沿计数半满标志
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wire full_div_n; //下降沿计数满标志
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wire half_div_n; //下降沿计数半满标志
38![](/Images/OutliningIndicators/None.gif)
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//判断计数标志位置位与否
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assign full_div_p = (count_p < F_DIV - 1);
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assign half_div_p = (count_p < (F_DIV>>1) - 1);
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assign full_div_n = (count_n < F_DIV - 1);
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assign half_div_n = (count_n < (F_DIV>>1) - 1);
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//时钟输出
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assign clk_out = (F_DIV == 1) ?
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clock : (F_DIV[0] ? (clk_p_r & clk_n_r) : clk_p_r); //F_DIV[0]用于判断奇偶数
48![](/Images/OutliningIndicators/None.gif)
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//上升沿脉冲计数
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always @(posedge clock)
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begin
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if(full_div_p)
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begin
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count_p <= count_p + 1'b1;
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if(half_div_p)
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clk_p_r <= 1'b0;
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else
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clk_p_r <= 1'b1;
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end
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else
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begin
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count_p <= 0;
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clk_p_r <= 1'b0;
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end
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end
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//下降沿脉冲计数
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always @(negedge clock)
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begin
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if(full_div_n)
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begin
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count_n <= count_n + 1'b1;
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if(half_div_n)
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clk_n_r <= 1'b0;
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else
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clk_n_r <= 1'b1;
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end
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else
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begin
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count_n <= 0;
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clk_n_r <= 1'b0;
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end
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end
84![](/Images/OutliningIndicators/None.gif)
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endmodule
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