【实战经验】Xilinx时钟从普通IO输出问题
Xilinx芯片的时钟信号从普通IO输出时,在map过程中会出错,对此有两种解决方案;
1.在ucf文件中,添加对应的约束文件;
例如【PIN "U0_1/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;】其中" "中的时需要从普通IO输出的时钟名称或者BUFG的输出脚;
2.使用ODDR原语;
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_1 (
.Q(clock_out), // 1-bit DDR output data
.C0(clock_in), // 1-bit clock input
.C1(~clock_in), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);