bottomup_flow实践

scan_blocks

# bottom up scan insertion flow
# scan replace the sub-blocks
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40

set designs {BLENDER RESET_BLOCK PCI_WFIFO PCI_CORE PARSER PCI_RFIFO RISC_CORE \
         CONTEXT_MEM SD_W_MUX SDRAM_WFIFO SDRAM_IF SDRAM_RFIFO PCI_W_MUX}

foreach design $designs {    
    # read in the mapped scan-replaced sub-block (no scan chains yet)
    read_ddc mapped/${design}.ddc
    current_design ${design}
    # Recommended scan settings for blocks
    set_dft_configuration  -fix_bus disable   #禁用三态总线自动修复
    set_scan_configuration -clock_mix no_mix
    set_scan_configuration -create_dedicated_scan_out_ports true
    set_scan_configuration -max_length 100
    # Specify terminal lockup latches (except for SDRAM_IF)
    if { $design != "SDRAM_IF" } {
      set_scan_configuration -insert_terminal_lockup true
    }
    # Specify block-level clocks
    set clk_ports [get_ports "*clk fifo_clk*" -quiet]
    if { [sizeof_collection $clk_ports] > 0 } {
      set_dft_signal -view exist -type ScanClock -port $clk_ports -timing {45 55}
    }
    # Specify block-level Resets
    set clk_ports [filter_collection [all_inputs] "full_name=~*rst_n||full_name=~*reset_n"]
    if { [sizeof_collection $clk_ports] > 0 } {
      set_dft_signal -view exist -type Reset -active 0 -port $clk_ports
    }
    # test_mode exists on some blocks
    set tm_ports [get_ports "test_mode" -quiet]
    if { [sizeof_collection $tm_ports] > 0 } {
      set_dft_signal -view exist -type Constant -active 1 -port test_mode
    }

    # Create test protocol

    create_test_protocol

    # Perform gate-level DFT checks

    redirect -tee reports/${design}_dft_drc.rpt {dft_drc}

    # Preview the block-level scan chains

    redirect -tee reports/${design}_preview_dft.rpt {preview_dft -show scan_clocks}

    # Insert the block-level scan structures

    set_dft_insertion_configuration -synthesis none -preserve_design true
    insert_dft

    # Obtain block-level estimate of test coverage

    redirect -tee reports/${design}_coverage.rpt {dft_drc -coverage_estimate}

    # Document what happened during scan insertion

    report_dft_signal -view spec  > reports/${design}_test.rpt
    report_dft_signal -view exist >> reports/${design}_test.rpt
    report_dft_configuration >> reports/${design}_test.rpt
    report_scan_state >> reports/${design}_test.rpt
    report_scan_path -view exist > reports/${design}_scan_path.rpt

    # Handoff the block

    # Avoid naming issues between tools

    change_names -rule verilog -hierarchy

    # Save out the gate-level scan netlist for the block

    write -f verilog -h -o tmax/${design}_gates.v

    # It is good practice to to save the .ddc file, too
    # For example, tools such as PT and PC would prefer this format

    write -format ddc -hierarchy -output mapped_scan/${design}.ddc

    # Don't save the test model for the RESET_BLOCK module - not to be used at top
    if { $design != "RESET_BLOCK" } {

    # Save the Test Model HERE

    write_test_model -format ddc -output test_models/${design}.ctlddc
    }

    # Save the updated protocol

    set test_stil_netlist_format verilog
    write_test_protocol -o tmax/${design}.spf

    # Everything has been saved, remove current design and free up memory

    remove_design -designs
}

 

scan_top

# Read test models in and link top-level design

# Note: Read in the gate level model for the RESET_BLOCK module
# and tell DFTC not to use a test model for that module

# Read the test model for each of the blocks
read_test_model test_models/BLENDER.ctlddc
read_test_model test_models/PCI_WFIFO.ctlddc
read_test_model test_models/PCI_CORE.ctlddc
read_test_model test_models/PARSER.ctlddc
read_test_model test_models/PCI_RFIFO.ctlddc
read_test_model test_models/RISC_CORE.ctlddc
read_test_model test_models/CONTEXT_MEM.ctlddc
read_test_model test_models/SD_W_MUX.ctlddc
read_test_model test_models/SDRAM_WFIFO.ctlddc
read_test_model test_models/SDRAM_IF.ctlddc
read_test_model test_models/SDRAM_RFIFO.ctlddc
read_test_model test_models/PCI_W_MUX.ctlddc

# Specify to use the test models for each of the block-level designs
# This should be the default but it appears to be needed in this case
use_test_model -true [get_designs *]

# Read the gate-level design for RESET_BLOCK and don't use the test model
read_ddc mapped_scan/RESET_BLOCK.ddc
use_test_model -false RESET_BLOCK

# Read the higher level ORCA_TOP design
read_ddc mapped/ORCA_TOP.ddc

# Read the top-level ORCA design 
read_ddc mapped/ORCA.ddc
current_design ORCA
link

# Specify pre-clock measure timing
set test_default_bidir_delay 0
set test_default_delay 0
set test_default_strobe 40

# Define Clocks, Resets and Test Holds
set_dft_signal -view exist -type ScanClock -port {pclk sys_clk sdr_clk} -timing {45 55}
set_dft_signal -view exist -type Reset -active 0 -port prst_n
set_dft_signal -view exist -type Constant -active 1 -port test_mode

# Specify Scan Signals
set_dft_signal -view spec -type ScanEnable -active 1 -port scan_en

for {set i 0} {$i < 6} {incr i} {
    set hookup_cell pad_iopad_$i
    set_dft_signal -view spec -port pad[$i] -type ScanDataIn -hookup_pin $hookup_cell/CIN
    set hookup_cell sdram_A_iopad_$i
    set_dft_signal -view spec -port sd_A[$i] -type ScanDataOut -hookup_pin $hookup_cell/I
    set_scan_path chain$i -view spec -scan_data_in pad[$i] -scan_data_out sd_A[$i] 
}

# Specify Bidiretional Pins to be input mode during scan
set_autofix_configuration -type bidirectional -method output

# Specify desired number of balanced scan chains here
set_scan_configuration -chain_count 6 -clock_mixing mix_clocks

# Specify RSS options here
set_dft_insertion_configuration -preserve_design_name true -synthesis none

# Create the test protocol
create_test_protocol
write_test_protocol -o tmax/ORCA.spf

# Perform gate-level DFT checks
redirect -tee reports/ORCA_dft_drc.rpt {dft_drc}

# Preview the scan architecture
redirect -tee reports/ORCA_preview_dft.rpt {preview_dft -show scan_clocks}

# Insert the DFT structures
insert_dft

# Obtain an estimate of the test coverage
redirect -tee reports/ORCA_coverage.rpt {dft_drc -coverage}

# Document what happened during scan insertion
report_dft_signal -view spec > reports/ORCA_test.rpt
report_dft_signal -view exist >> reports/ORCA_test.rpt
report_dft_configuration >> reports/ORCA_test.rpt
report_scan_state >> reports/ORCA_test.rpt
report_scan_path -view exist > reports/ORCA_scan_path.rpt

# Handoff the design

# Avoid naming issues between tools
change_names -rule verilog -hierarchy

# Save out the gate-level scan netlist
write -f verilog -o tmax/ORCA_scan.v {ORCA CLOCK_GEN ORCA_TOP}
write -f verilog -o tmax/RESET_BLOCK_gates.v {RESET_BLOCK}

# It is good practice to to save the .ddc file, too
# For example, tools such as PT and PC would prefer this format
write -format ddc -output mapped_scan/ORCA_scan.ddc {ORCA CLOCK_GEN ORCA_TOP}
write -format ddc -output mapped_scan/RESET_BLOCK.ddc {RESET_BLOCK}

# Save the updated protocol
set test_stil_netlist_format verilog
write_test_protocol -o tmax/ORCA.spf