scan chain的原理和实现——9.HSS flow (hierarchical scan synthesis)

Hierarchical scan synthesis

Hierarchical scan synthesis(HSS) 也称为bottom-up flow

 

 

test model

test model是给定块的测试体系结构的抽象（CTL写的） 

1.  write&read test model

#Write a CTL DDC model
write_test_model -o counter.ctlddc -format ddc
#Write an ASCIl CTL model
write_test_model -o counter.ctl -format ctl
#Write a design DDC(with Test Model attached)
write -format ddc -hier -o counterl_scan.ddc
#Read a Test Model
read_test_model counter.ctlddc -format ddc
#Read a design DDC(with Test Model attached)
read_ddc counter.ddc

##The default write/read format is ddc

2.  Linking a Test Model to a Library Cell

ASCII CTL Test Model可以link到RAM之类的库

如果库单元（或hardmacro）具有内置扫描链，则必须将CTL test model link到library.lib或design

#link Test Model --> library
read_lib  <lib_name>.lib  -test_model <cell_name>:<model_file>.ctl
#link Test Model --> design
read_test_model  -format ctl  -design <full_path_to_cell_name> <model_file>.ctl