AMD64 专业名词缩写

National Convention (符号约定)
DS:SI
A far pointer or logical address. The real address or segment descriptor specified by the segment register (DS in this example) is combined with the offset contained in the second register (SI in this example) to form a real or virtual address. (DS:SI 指向的地址：DS中的内容作为实际地址+ SI中的内容作为偏移地址).

名词缩写：
CPL current privilege level；
GPRs general-purpose registers；
MMX Multimedia Extensions, (64 bit, support integer and float pointing operations),x87 Floating-Point Programming—80-bit x87 registers and supports floating point;
operations on scalar data types.
SSE Streaming SIMD Extensions；

Definitions (X86的的某些定义)
AVX
Extension of the SSE instruction set supporting 128- and 256-bit vector (packed) operands. See Streaming SIMD Extensions.
AVX2
Extension of the AVX instruction subset that adds more support for 256-bit vector (mostly packed integer) operands and a few new SIMD instructions. See Streaming SIMD Extensions.
commit（提交）
To irreversibly write, in program order, an instruction’s result to software-visible storage, such as a register (including flags), the data cache, an internal write buffer, or memory. 按顺序将结果写入寄存器。
doubleword
Two words, or four bytes, or 32 bits.
double quadword
Eight words, or 16 bytes, or 128 bits. Also called octword.
GDT
Global descriptor table.
GIF
Global interrupt flag.
IDT
Interrupt descriptor table.
IGN
Ignored. Value written ignored by hardware. Value returned on a read is indeterminate. See reserved.
IRB
The virtual-8086 mode interrupt-redirection bitmap.
IST
The long-mode interrupt-stack table.
IVT
The real-address mode interrupt-vector table.
LDT
Local descriptor table.
lsb
Least-significant bit.
LSB
Least-significant byte.
MBZ
Must be zero. If software attempts to set an MBZ bit to 1, a general-protection exception (#GP) occurs. See reserved.
msb Most-significant bit.
MSB Most-significant byte.
multimedia instructions
Those instructions that operate simultaneously on multiple elements within a vector data type. Comprises the 256-bit media instructions, 128-bit media instructions, and 64-bit media instructions.
PAE Physical-address extensions.
probe
A check for an address in a processor’s caches or internal buffers. External probes originate outside the processor, and internal probes originate within the processor.
RAZ
Read as zero. Value returned on a read is always zero (0) regardless of what was previously written. (See reserved)
vector
(1) A set of integer or floating-point values, called elements, that are packed into a single operand. Most of the media instructions support vectors as operands. Vectors are also called packed or SIMD (single-instruction multiple-data) operands.
(2) An index into an interrupt descriptor table (IDT), used to access exception handlers. Compare exception.

Registers
AH–DH
The high 8-bit AH, BH, CH, and DH registers. Compare AL–DL.
AL–DL
The low 8-bit AL, BL, CL, and DL registers. Compare AH–DH.
AL–r15B
The low 8-bit AL, BL, CL, DL, SIL, DIL, BPL, SPL, and R8B–R15B registers, available in 64-bit mode.
BP
Base pointer register.
CRn
Control register number n.
CS
CeAX–eSP
The 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers. Compare rAX–rSP.
EFER
Extended features enable register.
eFLAGS
16-bit or 32-bit flags register. Compare rFLAGS.
EFLAGS
32-bit (extended) flags register.
eIP
16-bit or 32-bit instruction-pointer register. Compare rIP.
EIP
32-bit (extended) instruction-pointer register.ode segment register
FLAGS
16-bit flags register.
GDTR
Global descriptor table register.
GPRs
General-purpose registers. For the 16-bit data size, these are AX, BX, CX, DX, DI, SI, BP, and SP. For the 32-bit data size, these are EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP. For the 64-bit data size, these include RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, and R8–R15.
IDTR
Interrupt descriptor table register.
IP
16-bit instruction-pointer register.
LDTR
Local descriptor table register.
MSR
Model-specific register.
r8–r15
The 8-bit R8B–R15B registers, or the 16-bit R8W–R15W registers, or the 32-bit R8D–R15D registers, or the 64-bit R8–R15 registers.
rAX–rSP
The 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers, or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers, or the 64-bit RAX, RBX, RCX, RDX, RDI, RSI, RBP, and RSP registers. Replace the placeholder r with nothing for 16-bit size, “E” for 32-bit size, or “R” for 64-bit size.
RAX
64-bit version of the EAX register.
RBP
64-bit version of the EBP register.
RBX
64-bit version of the EBX register.
RCX
64-bit version of the ECX register.
RDI
64-bit version of the EDI register.
RDX
64-bit version of the EDX register.
rFLAGS
16-bit, 32-bit, or 64-bit flags register. Compare RFLAGS.
RFLAGS
64-bit flags register. Compare rFLAGS.
rIP
16-bit, 32-bit, or 64-bit instruction-pointer register. Compare RIP.
RIP
64-bit instruction-pointer register.
RSI
64-bit version of the ESI register.
RSP
64-bit version of the ESP register.
SP
Stack pointer register.
SS
Stack segment register.
TPR
Task priority register (CR8), a new register introduced in the AMD64 architecture to speed interrupt management.
TR
Task register.