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Matlab实现抽样定理 - Wsine - 博客园 (cnblogs.com) clear all clc %% 设置原始信号 %t = -0.2 : 0.0005 : 0.2; t = -0.2 : (1/80) : 0.2; N = 1000; k = -N : N; W = k * 2000 阅读全文
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https://s2.smu.edu/~manikas/CAD_Tools/Verilog/SimVision_Tutorial_2013Jun.pdf 阅读全文
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https://www.5gtechnologyworld.com/the-basics-of-5gs-modulation-ofdm/ 搜索关键字 Candence NC-Verilog simulator Tutorial for Cadence SimVision Verilog Simula 阅读全文