verilog文件到tb的简单python脚本

使用

python3 verilog_to_tb.py
修改test.v为对应的文件。
需要注意的是，例化时并没有去掉最后的逗号，手动去除下。

verilog_to_tb.py(v2)

import re
def read_file(file):
    with open(file,'r') as f:
        lines = f.readlines()
    return lines
def main():
    lines = read_file('test.v')
    inp = re.compile(r'input\s+(\[(\d+):0\])?\s*(\w*)(,|;)?')
    outp = re.compile(r'output\s+(?:reg\s+)?(\[(\d+):0\])?\s*(\w*)(,|;)?')
    reg_line = []#将所有输入声明为reg
    wire_line = []#将所有输出声明为wire
    initial_line = []#将所有输入进行初始化，主要进行一些固定参数的配置
    module_line = ''#找module名
    ins_input = []#例化input
    ins_output = []#例化output
    for line in lines:
        match_result = inp.search(line)
        if(match_result):
            reg_line.append('reg '+ (match_result.group(1) if match_result.group(1) else '')+ match_result.group(3)+';')
            initial_line.append('    assign  '+match_result.group(3)+'='+(str(int(match_result.group(2))+1) if match_result.group(2) else '1')+'\'b0;')
            ins_input.append('     .'+match_result.group(3)+'('+match_result.group(3)+ \
                        (match_result.group(1) if match_result.group(1) else '')+'),')
            
        match_result = outp.search(line)
        if(match_result):
            wire_line.append('wire '+ (match_result.group(1) if match_result.group(1) else '')+ match_result.group(3)+';')
            ins_output.append('     .'+match_result.group(3)+'('+match_result.group(3)+ \
                        (match_result.group(1) if match_result.group(1) else '')+'),')
        if('module' in line and 'end' not in line):
            module_line = re.sub(r'module\s+(\w*)\(',r'\1 u_\1 (',line)
    for line in reg_line:
        print(line)
    for line in wire_line:
        print(line)
    print('initial')
    print('begin')
    for line in initial_line:
        print(line)
    print('end')
    print(module_line)
    print("  //input ports")
    for line in ins_input:
        print(line)
    print("  //output ports")
    for line in ins_output:
        print(line)
    print(');')
if __name__=="__main__":
    main()

verilog_to_tb.py(v1)

import re
def read_file(file):
    with open(file,'r') as f:
        lines = f.readlines()
    return lines
def main():
    lines = read_file('test.v')
    inp = re.compile(r'input\s+(\[(\d+):0\])?\s*(\w*)(,|;)?')
    outp = re.compile(r'output\s+(?:reg\s+)?(\[(\d+):0\])?\s*(\w*)(,|;)?')
    for line in lines:#将所有输入声明为reg
        match_result = inp.search(line)
        if(match_result):
            print('reg',end=' ')
            if match_result.group(1):
                print(match_result.group(1),end=' ')
            print(match_result.group(3)+';')
    for line in lines:#将所有输出声明为wire
        match_result = outp.search(line)
        if(match_result):
            print('wire',end=' ')
            if match_result.group(1):
                print(match_result.group(1),end=' ')
            print(match_result.group(3)+';')
    print('initial')
    print('begin')
    for line in lines:#将所有输入进行初始化，主要进行一些固定参数的配置
        match_result = inp.search(line)
        if(match_result):
            print('    assign',end=' ')
            if match_result.group(1):
                print(match_result.group(3)+'='+str(int(match_result.group(2))+1)+'\'b0;') 
            else:
                print(match_result.group(3)+'='+'1\'b0;')
    print('end')
    for line in lines:#找module名
        if('module' in line and 'end' not in line):
            print(re.sub(r'module\s+(\w*)\(',r'\1 u_\1 (',line),end='') 
            break
    print("  //input ports")
    for line in lines:
        match_result = inp.search(line)
        if(match_result):
            print('     .'+match_result.group(3)+'('+match_result.group(3)+ \
                        (match_result.group(1) if match_result.group(1) else '')+'),')#例化时加入input口

    print("  //output ports")
    for line in lines:
        match_result = outp.search(line)
        if(match_result):
            print('     .'+match_result.group(3)+'('+match_result.group(3)+ \
                        (match_result.group(1) if match_result.group(1) else '')+'),') #例化时加入output口
    print(');')
if __name__=="__main__":
    main()