8b10b编码 verilog
参考网址[https://asics.chuckbenz.com/]
8bit与10bit对应图
包含255个D码与12个K码，K码常用作控制字符。常表示为D.x.y或K.x.y（x为低5位的值，y为高3位的值）。
disparity表示当前0,1个数状态。0表示当前0的个数>=1的个数，1表示1的个数>=0的个数。
a7与p7
当KD共用x码值(23,27,29,30)时，通过高3位区分，D码使用备用P7编码，K码使用A7编码。
其余情况下，根据5b6b的译码结果决定使用p7还是a7，避免出现连续的0或者1。
经过观察，只有D.17.7，D.18.7，D.20.7和所有的K码使用A7编码，其余情况下都使用P7。
encode
输入变化前的disparity，data_in，输出data_out，变化后的disparity。
其中data_in为9bit数，最高位表示是否为k码，低8bit为8bit编码。
以9'b0_0000_0000，disparity=0为例，
首先取低5位，为00000，此时disparity为0，查表5b6b编码为100111。
100111中1的个数大于0的个数，所以需要disparity翻转为1。
高3位为000，此时disparity为1，3b4b编码为0100。
0100中0的个数大于1的个数，此时disparity翻转为0。
所以最后输出10bit数1001110100（可能需要翻转高低位），disparity为1。
disparity这种两步的变换可以简化为一步，encode得到的10bit中0,1个数不等时，进行翻转，否则不翻转。
disparity变化条件
当前的disparity为0时，进行5b6b或者3b4b编码时，选择的编码一定是1的个数>=0的个数。、
选择编码1的个数>0的个数时，disparity翻转，否则不翻转。
当前的disparity为1时，进行5b6b或者3b4b编码时，选择的编码一定是0的个数>=1的个数。、
选择编码0的个数>1的个数时，disparity翻转，否则不翻转。
decode
输入当前disparity，10bit数，输出code_err，disp_err，变化后的disparity，9bit数。
当当前10bit码不存在对应的8bit码时，code_err拉高。
当当前disparity为0且10bit数中0的个数大于1的个数时，或disparity为1且10bit数中1的个数大于0的个数时，disp_err拉高。
当前disparity相同时，变化后的disparity应与encode的变化后disparity相同。
源码转载:
encode.v
// Chuck Benz, Hollis, NH Copyright (c)2002
//
// The information and description contained herein is the
// property of Chuck Benz.
//
// Permission is granted for any reuse of this information
// and description as long as this copyright notice is
// preserved. Modifications may be made as long as this
// notice is preserved.
// per Widmer and Franaszek
module encode (datain, dispin, dataout, dispout) ;
input [8:0] datain ;
input dispin ; // 0 = neg disp; 1 = pos disp
output [9:0] dataout ;
output dispout ;
wire ai = datain[0] ;
wire bi = datain[1] ;
wire ci = datain[2] ;
wire di = datain[3] ;
wire ei = datain[4] ;
wire fi = datain[5] ;
wire gi = datain[6] ;
wire hi = datain[7] ;
wire ki = datain[8] ;
wire aeqb = (ai & bi) | (!ai & !bi) ;
wire ceqd = (ci & di) | (!ci & !di) ;
wire l22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd) ;
wire l40 = ai & bi & ci & di ;
wire l04 = !ai & !bi & !ci & !di ;
wire l13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi) ;
wire l31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi) ;
// The 5B/6B encoding
wire ao = ai ;
wire bo = (bi & !l40) | l04 ;
wire co = l04 | ci | (ei & di & !ci & !bi & !ai) ;
wire do = di & ! (ai & bi & ci) ;
wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ;
wire io = (l22 & !ei) |
(ei & !di & !ci & !(ai&bi)) | // D16, D17, D18
(ei & l40) |
(ki & ei & di & ci & !bi & !ai) | // K.28
(ei & !di & ci & !bi & !ai) ;
// pds16 indicates cases where d-1 is assumed + to get our encoded value
wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ;
// nds16 indicates cases where d-1 is assumed - to get our encoded value
wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ;
// ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
wire ndos6 = pd1s6 ;
// pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
wire pdos6 = ki | (ei & !l22 & !l13) ;
// some Dx.7 and all Kx.7 cases result in run length of 5 case unless
// an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
// specifically, D11, D13, D14, D17, D18, D19.
wire alt7 = fi & gi & hi & (ki |
(dispin ? (!ei & di & l31) : (ei & !di & l13))) ;
wire fo = fi & ! alt7 ;
wire go = gi | (!fi & !gi & !hi) ;
wire ho = hi ;
wire jo = (!hi & (gi ^ fi)) | alt7 ;
// nd1s4 is cases where d-1 is assumed - to get our encoded value
wire nd1s4 = fi & gi ;
// pd1s4 is cases where d-1 is assumed + to get our encoded value
wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ;
// ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
wire ndos4 = (!fi & !gi) ;
// pdos4 is nd1s4 cases where d-1 is - yields + disp out
wire pdos4 = fi & gi & hi ;
// only legal K codes are K28.0->.7, K23/27/29/30.7
// K28.0->7 is ei=di=ci=1,bi=ai=0
// K23 is 10111
// K27 is 11011
// K29 is 11101
// K30 is 11110 - so K23/27/29/30 are ei & l31
wire illegalk = ki &
(ai | bi | !ci | !di | !ei) & // not K28.0->7
(!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7
// now determine whether to do the complementing
// complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ;
// disparity out of 5b6b is disp in with pdso6 and ndso6
// pds16 indicates cases where d-1 is assumed + to get our encoded value
// ndos6 is cases where d-1 is + yields - disp out
// nds16 indicates cases where d-1 is assumed - to get our encoded value
// pdos6 is cases where d-1 is - yields + disp out
// disp toggles in all ndis16 cases, and all but that 1 nds16 case
wire disp6 = dispin ^ (ndos6 | pdos6) ;
wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ;
assign dispout = disp6 ^ (ndos4 | pdos4) ;
assign dataout = {(jo ^ compls4), (ho ^ compls4),
(go ^ compls4), (fo ^ compls4),
(io ^ compls6), (eo ^ compls6),
(do ^ compls6), (co ^ compls6),
(bo ^ compls6), (ao ^ compls6)} ;
endmodule
decode.v
// Chuck Benz, Hollis, NH Copyright (c)2002
//
// The information and description contained herein is the
// property of Chuck Benz.
//
// Permission is granted for any reuse of this information
// and description as long as this copyright notice is
// preserved. Modifications may be made as long as this
// notice is preserved.
// per Widmer and Franaszek
module decode (datain, dispin, dataout, dispout, code_err, disp_err) ;
input [9:0] datain ;
input dispin ;
output [8:0] dataout ;
output dispout ;
output code_err ;
output disp_err ;
wire ai = datain[0] ;
wire bi = datain[1] ;
wire ci = datain[2] ;
wire di = datain[3] ;
wire ei = datain[4] ;
wire ii = datain[5] ;
wire fi = datain[6] ;
wire gi = datain[7] ;
wire hi = datain[8] ;
wire ji = datain[9] ;
wire aeqb = (ai & bi) | (!ai & !bi) ;
wire ceqd = (ci & di) | (!ci & !di) ;
wire p22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd) ;
wire p13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi) ;
wire p31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi) ;
wire p40 = ai & bi & ci & di ;
wire p04 = !ai & !bi & !ci & !di ;
wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31.
wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits
wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits
wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 |
(ei & ii & di)) & (ei | ii | di)) ;
// The 5B/6B decoding special cases where ABCDE != abcde
wire p22bceeqi = p22 & bi & ci & (ei == ii) ;
wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ;
wire p13in = p13 & !ii ;
wire p31i = p31 & ii ;
wire p13dei = p13 & di & ei & ii ;
wire p22aceeqi = p22 & ai & ci & (ei == ii) ;
wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ;
wire p13en = p13 & !ei ;
wire anbnenin = !ai & !bi & !ei & !ii ;
wire abei = ai & bi & ei & ii ;
wire cdei = ci & di & ei & ii ;
wire cndnenin = !ci & !di & !ei & !ii ;
// non-zero disparity cases:
wire p22enin = p22 & !ei & !ii ;
wire p22ei = p22 & ei & ii ;
//wire p13in = p12 & !ii ;
//wire p31i = p31 & ii ;
wire p31dnenin = p31 & !di & !ei & !ii ;
//wire p13dei = p13 & di & ei & ii ;
wire p31e = p31 & ei ;
wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi |
p13en | abei | cndnenin ;
wire compb = p22bceeqi | p31i | p13dei | p22aceeqi |
p13en | abei | cndnenin ;
wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi |
p13en | anbnenin | cndnenin ;
wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi |
p13en | abei | cndnenin ;
wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi |
p13en | anbnenin | cndnenin ;
wire ao = ai ^ compa ;
wire bo = bi ^ compb ;
wire co = ci ^ compc ;
wire do = di ^ compd ;
wire eo = ei ^ compe ;
wire feqg = (fi & gi) | (!fi & !gi) ;
wire heqj = (hi & ji) | (!hi & !ji) ;
wire fghj22 = (fi & gi & !hi & !ji) |
(!fi & !gi & hi & ji) |
( !feqg & !heqj) ;
wire fghjp13 = ( !feqg & !hi & !ji) |
( !heqj & !fi & !gi) ;
wire fghjp31 = ( (!feqg) & hi & ji) |
( !heqj & fi & gi) ;
wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ;
wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) |
(p13 & !ei & ii & gi & hi & ji) |
(p31 & ei & !ii & !gi & !hi & !ji)) ;
wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1
((dispin & ci & di & !ei & !ii) | ko |
(dispin & !ci & di & !ei & !ii))) |
(!fi & gi & hi & // 0111 cases, where disp6b is 0
(( !dispin & !ci & !di & ei & ii) | ko |
( !dispin & ci & !di & ei & ii))) ;
wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ;
// k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
wire k28p = ! (ci | di | ei | ii) ;
wire fo = (ji & !fi & (hi | !gi | k28p)) |
(fi & !ji & (!hi | gi | !k28p)) |
(k28p & gi & hi) |
(!k28p & !gi & !hi) ;
wire go = (ji & !fi & (hi | !gi | !k28p)) |
(fi & !ji & (!hi | gi |k28p)) |
(!k28p & gi & hi) |
(k28p & !gi & !hi) ;
wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) |
(fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) |
(!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ;
wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ;
wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ;
wire disp4p = fghjp31 ;
wire disp4n = fghjp13 ;
assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) |
(p13 & !ei & !ii) | (p31 & ei & ii) |
(ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) |
(ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) |
(!p31 & ei & !ii & !gi & !hi & !ji) |
(!p13 & !ei & ii & gi & hi & ji) |
(((ei & ii & !gi & !hi & !ji) |
(!ei & !ii & gi & hi & ji)) &
! ((ci & di & ei) | (!ci & !di & !ei))) |
(disp6p & disp4p) | (disp6n & disp4n) |
(ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) |
(!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) |
(fi & gi & !hi & !ji & disp6p) |
(!fi & !gi & hi & ji & disp6n) |
(ci & di & ei & ii & !fi & !gi & !hi) |
(!ci & !di & !ei & !ii & fi & gi & hi) ;
assign dataout = {ko, ho, go, fo, eo, do, co, bo, ao} ;
// my disp err fires for any legal codes that violate disparity, may fire for illegal codes
assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) |
(dispin & !disp6n & fi & gi) |
(dispin & ai & bi & ci) |
(dispin & !disp6n & disp4p) |
(!dispin & !disp6p & !fi & !gi) |
(!dispin & !ai & !bi & !ci) |
(!dispin & !disp6p & disp4n) |
(disp6p & disp4p) | (disp6n & disp4n)) ;
endmodule
testbench
// Chuck Benz, Hollis, NH Copyright (c)2002
//
// The information and description contained herein is the
// property of Chuck Benz.
//
// Permission is granted for any reuse of this information
// and description as long as this copyright notice is
// preserved. Modifications may be made as long as this
// notice is preserved.
// 11-OCT-2002: updated with clearer messages, and checking decodeout
`timescale 1ns / 1ns
module test_8b10b ;
reg [29:0] code8b10b [0:267] ;
reg [8:0] testin ;
reg dispin ;
reg [10:0] i ;
wire [9:0] testout ;
wire dispout, decodedisp, decodeerr, disperr ;
wire [8:0] decodeout ;
// My data file is 30 columns. Column 1 becomes [29], 2 becomes [28], etc..
// code[0] is last Column (30)
// First column, [29] is K indication
// columns 2:9, [28:21], are data byte, aka 'm' and 'n' of Dm.n
// columns 10:19, [20:11] are 10b symbol if starting disparity was negative, 0
// columns 20:29, [10:1] are 10b symbol if starting disparity was positive, 1
// column 30, [0], is a 1 if symbol results in a disparity flip
// 0 for a balanced symbol (5 '1's, 5 '0's).
wire [29:0] code = code8b10b[i] ;
wire [9:0] expect_0_disp = {code[11], code[12], code[13], code[14], code[15],
code[16], code[17], code[18], code[19], code[20]} ;
wire [9:0] expect_1_disp = {code[1], code[2], code[3], code[4], code[5],
code[6], code[7], code[8], code[9], code[10]} ;
reg [1023:0] legal ; // mark every used 10b symbol as legal, leave rest marked as not
reg [2047:0] okdisp ; // now mark every used combination of symbol and starting disparity
reg [8:0] mapcode [1023:0] ;
reg [10:0] codedisp0, codedisp1 ;
reg [9:0] decodein ;
reg decdispin ;
integer errors ;
encode DUTE (testin, dispin, testout, dispout) ;
decode DUTD (decodein, decdispin, decodeout, decodedisp, decodeerr, disperr) ;
always @ (code) testin = code[29:21] ;
initial begin
errors = 0 ;
$readmemb ("8b10b_a.mem", code8b10b) ;
//$vcdpluson ;
$dumpvars (0);
$display ("\n\nFirst, test by trying all 268 (256 Dx.y and 12 Kx.y)") ;
$display ("valid inputs, with both + and - starting disparity.");
$display ("We check that the encoder output and ending disparity is correct.");
$display ("We also check that the decoder matches.");
for (i = 0 ; i < 268 ; i = i + 1) begin
// testin = code[29:21] ;
dispin = 0 ;
#1
decodein = testout ;
decdispin = dispin ;
#1
// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ;
if (testout != expect_0_disp)
$display ("bad code0 %b %b %b %b %b", dispin, testin, dispout, testout, expect_0_disp) ;
if (dispout != (dispin ^ code[0]))
$display ("bad disp0 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ;
if (0 != (9'b1_1111_1111 & (testin ^ decodeout)))
$display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ;
if (decodedisp != dispout)
$display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ;
if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ;
if ((testout != expect_0_disp) | decodeerr |
(dispout != (dispin ^ code[0])) | (decodedisp != dispout))
errors = errors + 1 ;
dispin = 1 ;
#1
decodein = testout ;
decdispin = dispin ;
#1
// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2, DUTD.fghjp31, DUTD.feqg, DUTD.heqj, DUTD.fghj22, DUTD.fi, DUTD.gi, DUTD.hi, DUTD.ji, DUTD.dispout}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ;
if (testout != expect_1_disp)
$display ("bad code1 %b %b %b %b %b", dispin, testin, dispout, testout, expect_1_disp) ;
if (dispout != (dispin ^ code[0]))
$display ("bad disp1 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ;
if (0 != (9'b1_1111_1111 & (testin ^ decodeout)))
$display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ;
if (decodedisp != dispout)
$display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ;
if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ;
if ((testout != expect_1_disp) | decodeerr |
(dispout != (dispin ^ code[0])) | (decodedisp != dispout))
errors = errors + 1 ;
end
$display ("%d errors in that testing.\n", errors) ;
// Now, having verified all legal codes, lets run some illegal codes
// at the decoder... how to figure illegal codes ? 2048 possible cases,
// lets mark the OK ones...
legal = 0 ;
okdisp = 0 ;
for (i = 0 ; i < 268 ; i = i + 1) begin
#1
// $display ("i=%d: %b %b %d %d %x %x", i, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp) ;
legal[expect_0_disp] = 1 ;
legal[expect_1_disp] = 1 ;
codedisp0 = expect_0_disp ;
codedisp1 = {1'b1, expect_1_disp} ;
okdisp[codedisp0] = 1 ;
okdisp[codedisp1] = 1 ;
mapcode[expect_0_disp] = code[29:21] ;
mapcode[expect_1_disp] = code[29:21] ;
end
$display ("Now lets test all (legal and illegal) codes into the decoder.");
$display ("checking all possible decode inputs") ;
for (i = 0 ; i < 1024 ; i = i + 1) begin
decodein = i ;
decdispin = 0 ;
codedisp1 = 1024 | i ;
#1
if (((legal[i] == 0) & (decodeerr != 1)) |
(legal[i] & (mapcode[i] != decodeout)) |
(legal[i] & (disperr != !okdisp[i])))
$display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:",
decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i]) ;
if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ;
if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ;
if (legal[i] & (disperr != 1) & !okdisp[i]) $display ("ERR: disp err should be asserted") ;
else if (legal[i] & (disperr != 0) & okdisp[i])
$display ("ERR: disp err should not be asserted") ;
if (((legal[i] == 0) & (decodeerr != 1)) |
(legal[i] & !disperr & !okdisp[i]) |
(legal[i] & (mapcode[i] != decodeout)) |
(legal[i] & disperr & okdisp[i]))
errors = errors + 1 ;
decdispin = 1 ;
#1
if (((legal[i] == 0) & (decodeerr != 1)) |
(legal[i] & (mapcode[i] != decodeout)) |
(legal[i] & (disperr != !okdisp[i|1024])))
$display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:",
decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i|1024]) ;
if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ;
if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ;
if (legal[i] & (disperr != 1) & !okdisp[i|1024]) $display ("ERR: disp err should be asserted") ;
else if (legal[i] & (disperr != 0) & okdisp[i|1024])
$display ("ERR: disp err should not be asserted") ;
if (((legal[i] == 0) & (decodeerr != 1)) |
(legal[i] & !disperr & !okdisp[i|1024]) |
(legal[i] & (mapcode[i] != decodeout)) |
(legal[i] & disperr & okdisp[i|1024]))
errors = errors + 1 ;
end // for (i = 0 ; i < 1024 ; i = i + 1)
$display ("\nDone testing decoder.\n") ;
$display ("Total error count: %d", errors);
if (errors == 0) $display ("Congratulations!\n");
$finish ;
end // initial begin
endmodule
8b10b_a.mem(30bit的解释见testbench)
0_00000000_1001110100_0110001011_0
0_00000001_0111010100_1000101011_0
0_00000010_1011010100_0100101011_0
0_00000011_1100011011_1100010100_1
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