MMCM and PLL Dynamic Reconfiguration

 

Reconfiguration is performed through the DRP.

The DRP provides access to the configuration bits that would normally only be initialized in the bitstream. This allows the user to dynamically change the MMCM or PLL clock outputs without loading a new bitstream.

The MMCM or PLL must be held in reset during dynamic reconfiguration or must be reset after the dynamic reconfiguration changes have completed. Frequency, phase, and duty cycle can all be changed through the DRP port.

 

The MMCM has six user-accessible configuration bit groups that allow reconfiguration of individual clock outputs. The six groups are the divider group, the phase group, the fractional group, the lock group, the filter group, and the power group. These configuration bit groups are internal to the MMCM primitive and clarify the operation of the MMCM_DRP reference design module.

Below is the reconfiguration timing from simulation. 

 

 Please refer xapp888 and ug472 for more detailed informations.