CPU设计开发--取指模块
话不多说，时间不多了；
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1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: 4 -- 5 -- Create Date: 22:00:31 11/08/2012 6 -- Design Name: 7 -- Module Name: Get_IR - Behavioral 8 -- Project Name: 9 -- Target Devices: 10 -- Tool versions: 11 -- Description: 12 -- 13 -- Dependencies: 14 -- 15 -- Revision: 16 -- Revision 0.01 - File Created 17 -- Additional Comments: 18 -- 19 ---------------------------------------------------------------------------------- 20 library IEEE; 21 use IEEE.STD_LOGIC_1164.ALL; 22 use IEEE.STD_LOGIC_ARITH.ALL; 23 use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 25 ---- Uncomment the following library declaration if instantiating 26 ---- any Xilinx primitives in this code. 27 library UNISIM; 28 --use UNISIM.VComponents.all; 29 30 entity Get_IR is 31 port(t0,t1,t2 : in std_logic; 32 clk : in std_logic; 33 rst : in std_logic; 34 r : out std_logic; 35 MAR : out std_logic_vector(15 downto 0); 36 MDR : in std_logic_vector(15 downto 0); 37 PC_Updata: in std_logic; 38 IR_out: out std_logic_vector(15 downto 0); 39 PC_NEW: in std_logic_vector(15 downto 0) 40 ); 41 end Get_IR; 42 43 architecture Behavioral of Get_IR is 44 signal PC : std_logic_vector(15 downto 0); 45 begin 46 47 process(t0,t1,t2,rst,clk) 48 begin 49 if(rst='1')then 50 r<='0'; 51 PC<="0000000000000000"; 52 53 elsif(t0='1')then 54 MAR<=PC; 55 r<='1'; 56 57 elsif(t1='1')then 58 59 PC<=PC+1; 60 61 IR_out<=MDR; 62 63 elsif(t2='1' and PC_Updata='1')then 64 PC<=PC_NEW; 65 66 67 else null; 68 69 end if; 70 71 end process; 72 73 74 end Behavioral;
自己建立波形，然后运行结果如下：
看出来什么了么？
哈哈，注意一下PC，按照原意是每次PC自动加1，结果出现的运行结果并非我们所要的。。。。。这也是我想强调的一点，大家可以试试用下面这个代码，
具体为什么下面这个代码可以正常运行，我就不解释了，有点麻烦。
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1 ---------------------------------------------------------------------------------- 2 -- Company: 3 -- Engineer: 4 -- 5 -- Create Date: 22:00:31 11/08/2012 6 -- Design Name: 7 -- Module Name: Get_IR - Behavioral 8 -- Project Name: 9 -- Target Devices: 10 -- Tool versions: 11 -- Description: 12 -- 13 -- Dependencies: 14 -- 15 -- Revision: 16 -- Revision 0.01 - File Created 17 -- Additional Comments: 18 -- 19 ---------------------------------------------------------------------------------- 20 library IEEE; 21 use IEEE.STD_LOGIC_1164.ALL; 22 use IEEE.STD_LOGIC_ARITH.ALL; 23 use IEEE.STD_LOGIC_UNSIGNED.ALL; 24 25 ---- Uncomment the following library declaration if instantiating 26 ---- any Xilinx primitives in this code. 27 library UNISIM; 28 --use UNISIM.VComponents.all; 29 30 entity Get_IR is 31 port(t0,t1,t2 : in std_logic; 32 clk : in std_logic; 33 rst : in std_logic; 34 r : out std_logic; 35 MAR : out std_logic_vector(15 downto 0); 36 MDR : in std_logic_vector(15 downto 0); 37 PC_Updata: in std_logic; 38 IR_out: out std_logic_vector(15 downto 0); 39 PC_NEW: in std_logic_vector(15 downto 0) 40 ); 41 end Get_IR; 42 43 architecture Behavioral of Get_IR is 44 signal PC : std_logic_vector(15 downto 0); 45 begin 46 47 process(t0,t1,t2,rst,clk) 48 begin 49 if(rst='1')then 50 r<='0'; 51 PC<="0000000000000000"; 52 53 elsif(t0='1')then 54 MAR<=PC; 55 r<='1'; 56 57 --就在这儿修改了 58 elsif(t1='1')then 59 if(clk'event and clk='1' )then 60 PC<=PC+1; 61 end if; 62 IR_out<=MDR; 63 64 elsif(t2='1' and PC_Updata='1')then 65 PC<=PC_NEW; 66 67 68 else null; 69 70 end if; 71 72 end process; 73 74 75 end Behavioral;
哦哦，好使了吧，继续些别的了，加油。。。。。
更新：对了，也许有的同学运行的结果里面没有PC这个东东，怎么办呢
额，有兴趣的话去我另外一篇文章看看吧。
http://www.cnblogs.com/xubenben/archive/2012/11/09/ModelSim.html
