ZYNQ PS 复位PL FCLK_RESET0_N

ZYNQ 7000

PS Reset PL

PS 可以输出4个独立的复位信号给PL，用于控制PL逻辑的复位。

如何控制呢？

参考 https://support.xilinx.com/s/question/0D52E00006hpUDcSAM/asserting-fclkreset0n-fpgarstctrl-from-baremetal-system?language=en_US

裸机代码如下：

    // assert FPGA Reset Signal
#define XSLCR_BASEADDR					0xF8000000U
#define XSLCR_LOCK_ADDR				    (XSLCR_BASEADDR + 0x00000004U)
#define XSLCR_UNLOCK_ADDR				(XSLCR_BASEADDR + 0x00000008U)

#define XSLCR_FPGA_RST_CTRL_ADDR        (XSLCR_BASEADDR + 0x00000240U)

/**< SLCR unlock code */
#define XSLCR_LOCK_CODE		    0x0000767BU
#define XSLCR_UNLOCK_CODE		0x0000DF0DU

	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
    Xil_Out32(XSLCR_FPGA_RST_CTRL_ADDR, 0x0F);
 
    // do stuff
 
    // and release the FPGA Reset Signal
    Xil_Out32(XSLCR_FPGA_RST_CTRL_ADDR, 0x00);
    Xil_Out32(XSLCR_LOCK_ADDR, XSLCR_LOCK_CODE)；

system level registers , write lock and unlock first, then access the register

XSLCR_FPGA_RST_CTRL_ADDR

如何在Linux中控制呢？

通过devmem 访问寄存器绝对地址即可，示例如下

devmem 0xf8000008 32 0xdf0d

ZYNQ Ultrascale

同ZYNQ 7000类似，PS到PL有4路可用复位。可以参考PS_INIT.C中的代码去完成复位动作。但是实际上，这种操作都有些复杂，XILINX的工程师甚至也推荐用户干脆用GPIO搞一下就可以了。

https://support.xilinx.com/s/article/68962?language=en_US

https://support.xilinx.com/s/article/66220?language=en_US#:~:text=While using PS %2B PL designs%2C no dedicated,Alternatively%2C use fabric PLL lock signal as reset.

While using PS + PL designs, no dedicated reset signal is available to reset PL from PS. This answer record documents the work-around for this issue.

Use any of the pins from GPIO as a reset pin with software toggle. Alternatively, use fabric PLL lock signal as reset.

Additionally, while using xsdb as a debugger, please use following set of commands to toggle the GPIO to assert and de-assert reset


dow .<fsbl path>/fsbl.elf
stop
mwr 0xFF0A0018 0xFFFF0000    # Maskable Output Data (GPIO Bank3, EMIO, Lower 16bits)
mwr 0xFF0A02C4 0xFFFFFFFF  # Direction mode (GPIO Bank3, EMIO)
mwr 0xFF0A02C8 0xFFFFFFFF  # Output enable (GPIO Bank3, EMIO)
mwr 0xFF0A004C 0x00000001   # Output Data (GPIO Bank3, EMIO)  # writing 1 to EMIO GPIO 0                               
After 1000
#Assert reset (active low)
mwr 0xFF0A004C 0x00000000   # Output Data (GPIO Bank3, EMIO)  # writing 0 to EMIO GPIO 0     
After 1000
#De-assert reset (active high)
mwr 0xFF0A004C 0x00000001   # Output Data (GPIO Bank3, EMIO)  # writing 1 to EMIO GPIO 0     
Now download ELF file for the PS-PL application

This issue is expected to be fixed in the 2016.1 release.

可以看出来，上述复位控制写了多组寄存器来进行控制，相对比较复杂。所以还是推荐使用GPIO模块来完成。