1 IOB
为了保证FPGA输入输出接口的时序,一般会要求将输入管脚首先打一拍再使用,输出接口也要打一拍再输出FPGA。将信号打一拍的方法是将信号通过一次寄存器,而且必须在IOB里面的寄存器中打一拍。因为,从FPGA的PAD到IOB里面的寄存器是有专用布线资源的,而到内部其他寄存器没有专用的布线资源。使用IOB里面的寄存器可以保证每次实现的结果都一样,使用内部其他寄存器就无法保证每次用的都是同一个寄存器且采用同样的布线。同时,为了使用输入输出延迟功能(Input / Output delay),也必须要求信号使用IOB里面的寄存器。
为了让I/O使用IOB里面的寄存器,需要设定综合与MAP(对应于Xilinx的ISE工具)的相关属性。默认情况下,综合过程和MAP过程都是根据软件的分析自动判断是否要将I/O 的寄存器放入
IOBs中。如果需要强制指定,必须将Pack I/O Registe Into IOBs的默认属性修改成需要的值。对于XST,可以将I/O Pack Registers Into IOB属性由默认的Auto 修改为Yes或No。对于Snyplify,可以在Verilog代码的模块声明中添加属性:/* synthesis syn_useioff = 1 */。具体应用如下 module module_a(a,b,c) /* synthesis syn_useioff = 1 */ ; 。MAP过程Pack I/O
Registe Into IOBs属性可以设置成:Off,For Inputs Only,For Output Only,For Input and Output。需要特别注意的是,如果只在MAP过程中要求将I/O放入IOBs中,而在综合过程中没有强制要求,最终实现时I/O不一样会Pack Into IOBs。必须保证综合和MAP同时对该属性进行设定。
2 XST 综合错误报告修正 IBUFG
当输入时钟进入MMCME2_ADV时钟管理模块之前,用了IBUFG
clkin1_buf : IBUFG port map (O => clkin1, I => CLK_100);
-- Clocking primitive -------------------------------------- -- Instantiation of the MMCM primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused mmcm_adv_inst : MMCME2_ADV generic map (BANDWIDTH => "OPTIMIZED", CLKOUT4_CASCADE => FALSE, COMPENSATION => "ZHOLD", STARTUP_WAIT => FALSE, DIVCLK_DIVIDE => 1, CLKFBOUT_MULT_F => 10.000, CLKFBOUT_PHASE => 0.000, CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_DIVIDE_F => 10.000, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_USE_FINE_PS => FALSE, CLKOUT1_DIVIDE => 40, CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT1_USE_FINE_PS => FALSE, CLKIN1_PERIOD => 10.000, REF_JITTER1 => 0.010) port map -- Output clocks (CLKFBOUT => clkfbout, CLKFBOUTB => clkfboutb_unused, CLKOUT0 => clkout0, CLKOUT0B => clkout0b_unused, CLKOUT1 => clkout1, CLKOUT1B => clkout1b_unused, CLKOUT2 => clkout2_unused, CLKOUT2B => clkout2b_unused, CLKOUT3 => clkout3_unused, CLKOUT3B => clkout3b_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, CLKOUT6 => clkout6_unused, -- Input clock control CLKFBIN => clkfbout_buf, CLKIN1 => clkin1, CLKIN2 => '0', -- Tied to always select the primary input clock CLKINSEL => '1', -- Ports for dynamic reconfiguration DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DO => do_unused, DRDY => drdy_unused, DWE => '0', -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => psdone_unused, -- Other control and status signals LOCKED => locked_unused, CLKINSTOPPED => clkinstopped_unused, CLKFBSTOPPED => clkfbstopped_unused, PWRDWN => '0', RST => '0'); -- Output buffering ------------------------------------- clkf_buf : BUFG port map (O => clkfbout_buf, I => clkfbout); clkout1_buf : BUFG port map (O => CLK_50, I => clkout0); clkout2_buf : BUFG port map (O => CLK_25, I => clkout1);
ERROR:Xst:2035
- Port <CLK> has illegal connections. This port is connected to an input buffer and other components.
解决办法
选中synthesize,然后process->properties->Xilinx Specific Options,把add I/O buffer 的勾去掉。
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