verilog 24进制+60进制 模拟时钟计数器

1、RTL代码

module clock_24_60(
					clk,
					rst,
					hour_h,
					hour_l,
					minute_h,
					minute_l
					);
  
input         clk,rst;
output[3:0]   hour_h,hour_l,minute_h,minute_l;
reg[3:0]      hour_h,hour_l,minute_h,minute_l;
wire          cout;
 
//60进制低4位计数 
always @(posedge clk)
begin
  if(!rst)
        minute_l <= 0;
  else if(minute_l==9)
        minute_l <= 0;
  else 
        minute_l <= minute_l + 1;
end

//60进制高4位计数 
always @(posedge clk)
begin
  if(!rst)
        minute_h <= 0;
  else if(minute_l==9)
  begin
      if(minute_h==5)
        minute_h <= 0;
      else 
        minute_h <= minute_h + 1;
  end
end
 
assign cout = ((minute_l==9)&&(minute_h==5))?1:0;
//24进制低4位计数 
always @(posedge clk)
begin
  if(!rst)
        hour_l <= 0;
  else if(cout)
  begin
      if(hour_l==9)
        hour_l <= 0;
      else if((hour_l==3)&&(hour_h==2))
        hour_l <= 0;
      else
        hour_l <= hour_l + 1;
  end
end
 //24进制高4位计数 
always @(posedge clk)
begin
  if(!rst)
        hour_h <= 0;
  else if(cout)
  begin
      if((hour_l==3)&&(hour_h==2))
        hour_h <= 0;
      else if(hour_l==9)
        hour_h <= hour_h + 1;
  end
end
 
endmodule

2、仿真程序

module test;
  
reg clk, rst;
wire[3:0]   hour_h,hour_l,minute_h,minute_l;
 
clock_24_60 u1
                (
                .clk(clk),
                .rst(rst),
                .hour_h(hour_h),
                .hour_l(hour_l),
                .minute_h(minute_h),
                .minute_l(minute_l)
                );
                
always #5 clk = ~clk;
  
initial
begin
  clk = 0;
  rst = 0;
  #30  rst = 1;
end
 
endmodule 

3、仿真结果

由于需要计数很多次才能看到实际效果，所以这里就不演示了，感兴趣的可以自己多仿真一些时间。