2014年7月23日
FPGA quartus开发中常见的错误处理
摘要： 1.Warning: An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps wh... 阅读全文
posted @ 2014-07-23 00:23 wzd5230 阅读(4299) 评论(0) 推荐(0) 编辑