视频处理单元Video Processing Unit

视频处理单元Video Processing Unit

VPU处理全局视频处理，它包括时钟门、块复位线和电源域的管理。

 

缺少什么：

 

•完全重置整个视频处理硬件块

 

•VPU时钟的缩放和设置

 

•总线时钟门

 

•启动视频处理硬件块

 

•启动HDMI控制器和PHY

 

视频处理单元

 

显示控制器由以下几个组件组成：

DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|

   | vd1   _______     _____________    _________________     |               |

D  |-------|      |----|            |   |                |    |   HDMI PLL    |

D  | vd2   | VIU  |    | Video Post |   | Video Encoders |<---|-----VCLK      |

R  |-------|      |----| Processing |   |                |    |               |

   | osd2  |      |    |            |---| Enci ----------|----|-----VDAC------|

R  |-------| CSC  |----| Scalers    |   | Encp ----------|----|----HDMI-TX----|

A  | osd1  |      |    | Blenders   |   | Encl ----------|----|---------------|

M  |-------|______|----|____________|   |________________|    |               |

___|__________________________________________________________|_______________|

Video Input Unit

VIU handle像素扫描和基本颜色空间转换，包括以下功能：

OSD1 RGB565/RGB888/xRGB8888 scanout

• RGB conversion to x/cb/cr
• Progressive or Interlace buffer scanout
• OSD1 Commit on Vsync
• HDR OSD matrix for GXL/GXM

What is missing :

• BGR888/xBGR8888/BGRx8888/BGRx8888 modes
• YUV4:2:2 Y0CbY1Cr scanout
• Conversion to YUV 4:4:4 from 4:2:2 input
• Colorkey Alpha matching
• Big endian scanout
• X/Y reverse scanout
• Global alpha setup
• OSD2 support, would need interlace switching on vsync
• OSD1 full scaling to support TV overscan

Video Post Processing

VPP Handles有关VIU扫描后的所有后处理，包括以下模块:

• Postblend, Blends the OSD1 only

We exclude OSD2, VS1, VS1 and Preblend output

• Vertical OSD Scaler for OSD1 only, we disable vertical scaler and

use it only for interlace scanout

• Intermediate FIFO with default Amlogic values

What is missing :

• Preblend for video overlay pre-scaling
• OSD2 support for cursor framebuffer
• Video pre-scaling before postblend
• Full Vertical/Horizontal OSD scaling to support TV overscan
• HDR conversion

Video Encoder

VENC将像素编码处理为输出格式。包括以下编码 :

• CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
• TMDS/HDMI Encoding via ENCI_DIV and ENCP
• Setup of more clock rates for HDMI modes

What is missing :

• LCD Panel encoding via ENCL
• TV Panel encoding via ENCT

VENC paths :

       _____   _____   ____________________

vd1---|     |-|     | | VENC     /---------|----VDAC

vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|

osd1--|     |-|     | | \                  | X--HDMI-TX

osd2--|_____|-|_____| |  |\-ENCP--ENCP_DVI-|-|

                      |  |                 |

                      |  \--ENCL-----------|----LVDS

                      |____________________|

ENCI设计用于PAl或NTSC编码，可以直接通过VDAC进行CVBS编码，也可以通过ENCI\U DVI编码器，进行HDMI编码。ENCP设计用于渐进编码，但也可以生成1080i交错像素，最初设计用于对VDAC的像素编码，以输出RGB ou YUV模拟输出。输出通过用于HDMI的ENCP\U DVI编码器。ENCL LVDS编码器未实现。

ENCI和ENCP编码器，需要为每个支持的模式专门定义参数，因此不能从标准视频timings来确定。

ENCI-end-ENCP-DVI编码器更通用，可以从ENCI或ENCP生成的像素数据，生成任何时序，可以使用标准视频时序作为HW参数的源。

Video Clocks

VCLK是一个专用PLL的“像素时钟”频率发生器。包括以下编码：

CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks

• HDMI Pixel Clocks generation

What is missing :

• Genenate Pixel clocks for 2K/4K 10bit formats

Clock generator scheme :

 __________   _________            _____

|          | |         |          |     |--ENCI

| HDMI PLL |-| PLL_DIV |--- VCLK--|     |--ENCL

|__________| |_________| \        | MUX |--ENCP

                          --VCLK2-|     |--VDAC

                                  |_____|--HDMI-TX

Final clocks can take input for either VCLK or VCLK2, but VCLK is the preferred path for HDMI clocking and VCLK2 is the preferred path for CVBS VDAC clocking.

VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.

The PLL_DIV can achieve an additional fractional dividing like 1.5, 3.5, 3.75… to generate special 2K and 4K 10bit clocks.

HDMI Video Output

HDMI Output is composed of :

• A Synopsys DesignWare HDMI Controller IP
• A TOP control block controlling the Clocks and PHY
• A custom HDMI PHY in order convert video to TMDS signal

 ___________________________________

|            HDMI TOP               |<= HPD

|___________________________________|

|                  |                |

|  Synopsys HDMI   |   HDMI PHY     |=> TMDS

|    Controller    |________________|

|___________________________________|<=> DDC

HDMI机顶盒仅支持HPD感测。Synopsys HDMI控制器，中断顶部块中断路由。通过一对addr+read/write读/写寄存器以及顶层模块，与Synopsys HDMI控制器进行通信。HDMI PHY由HHI寄存器配置。

像素数据以4:4:4格式，从VENC块到达，VPU HDMI mux为576i或480i格式，选择ENCI编码器，或为所有其它格式（包括隔行高清格式），选择ENCP编码器。VENC使用ENCI或ENCP编码器顶部的DVI编码器，为HDMI控制器生成DVI定时。

GXBB、GXL和GXM嵌入了Synopsys DesignWare HDMI TX IP版本2.01a，带有HDCP和I2C&S/PDIF音频源接口。

It handle the following features :

• HPD Rise & Fall interrupt
• HDMI Controller Interrupt
• HDMI PHY Init for 480i to 1080p60
• VENC & HDMI Clock setup for 480i to 1080p60
• VENC Mode setup for 480i to 1080p60

What is missing :

• PHY, Clock and Mode setup for 2k && 4k modes
• SDDC Scrambling mode for HDMI 2.0a
• HDCP Setup
• CEC Management