Adding and using a new instruction

To add a new instruction to RISCV, we must add it to our compiler (riscv-gnu-toolchain for now) and whatever simulator/emulator we're using (spike for now).

First we follow the steps from Spike's setup page:

1. Describe the instruction's functional behavior in the package riscv-isa-sim, in riscv-isa-sim/riscv/insns/.h.
   Examine other instructions in that directory as a starting point.
2. Add the opcode and opcode mask to riscv-opcodes/opcodes. You can pick any open opcode, and there are several formats to choose from. Pick the type that fits your needs (source/destination registers, use of an immediate, etc.). riscv-opcodes/opcodes shows how two instructions, tagenforce and settag were inserted.
3. Run make install in riscv-opcodes.
4. This should have installed the opcode/masks necessary for your new instructions to all the proper header files.
   At the very least, check that a match and mask for your instruction have been generated and placed in
   riscv-isa-sim/riscv/encoding.h, riscv-gnu-toolchain/binutils/include/opcode/riscv-opc.h, and riscv-gnu-toolchain/gcc/gcc/config/riscv/riscv-opc.h.
   If your instruction interacts with the spike proxy kernel, also check riscv-pk/pk/encoding.h.
5. Finally, add structs for this instruction in the riscv_builtin_opcodes array in riscv-gnu-toolchain/binutils/opcodes/riscv-opc.h.
   The easiest way to do this is to find an existing instruction with the same instruction type as yours, and copy the formatting, replacing MATCH's and MASK's appropriately. As far as the strange letters signifying arguments go, this is currently how I understand them:
   d = uses rd
s = uses rs1
t = uses rs2
j = uses immediate12 - i-type instructions (also ‘o’?)
   u = uses immediate20 - u-type instructions (shifted down)
   a = uses immediate20 - uj-type instructions
   p = uses immediate12 - sb-type instructions
   q = uses immediate12 - s-type instructions
   d = uses immediate20 - u-type instructions (unshifted)
   z = uses zero register (always loads 0, stores do nothing)

Now, we need to add support for decoding this instruction to Spike:
6. In riscv-isa-sim/spike_main/disasm.cc, add a DEFINE_$TYPE call for your instruction, replacing $ with the appropriate instruction format (this should match the instruction format you used in riscv-opcodes/opcodes).
For uj-type instructions, you'll have to add the instruction manually, as there is no DEFINE macro available.
7. Give it a try! Try compiling a small program and running it in spike with your new instruction
(declared via __asm__ or __asm__ volatile).