基于Verilog的简单FIFO读写实验
一、模块框图及基本思路
fifo_ip:ISE生成的IP
fifo_control:在fifo未满情况下不断写入递增的四位数，每隔1s读出一个数据驱动Led显示
fifo_top:前两个模块的组合
二、软件部分
fifo_control:
1 module fifo_control( 2 clk,rst, 3 Data_Out, 4 din,wr_en,full, 5 dout,rd_en,empty 6 ); 7 input clk,rst; 8 output[3:0] Data_Out; 9 output [3:0] din; //相对fifo来说是输入 10 input [3:0] dout; //相对fifo来说是输出 11 output wr_en,rd_en; 12 input full,empty; 13 14 15 /****************定时部分*********************/ 16 localparam T1S=50_000_000-1; 17 reg[31:0] Count_1s; 18 always @(posedge clk or posedge rst) 19 begin 20 if(rst) 21 begin 22 Count_1s<=32'd0; 23 end 24 else if(Count_1s==T1S) 25 Count_1s<=32'd0; 26 else if(!isCount) 27 Count_1s<=32'd0; 28 else Count_1s<=Count_1s+1'b1; 29 end 30 /*****************FIFO写入部分********************/ 31 reg [1:0] i; 32 reg wr_en; 33 reg [3:0]din; 34 35 always @(posedge clk or posedge rst) 36 if(rst) 37 begin 38 din<=16'd0; 39 i<=2'd0; 40 wr_en<=1'b0; 41 end 42 else if(!full) 43 case(i) 44 2'd0:begin din<=din+1'b1;i<=i+1'b1;wr_en<=1'b1;end 45 2'd1:begin i<=2'd0;wr_en<=1'b0;end 46 endcase 47 /*******************FIFO读出部分***************************/ 48 reg[3:0] Data_Out_r; 49 wire [3:0] dout; 50 reg isCount; 51 reg [2:0]j; 52 reg rd_en; 53 54 always @(posedge clk or posedge rst) 55 if(rst) 56 begin 57 Data_Out_r<=4'd0; 58 j<=3'd0; 59 isCount<=1'b0; 60 rd_en<=1'b0; 61 end 62 else if(!empty) 63 case(j) 64 3'd0:if(Count_1s==T1S) begin j<=j+1'b1;isCount<=1'b0;rd_en<=1'b1; end 65 else isCount<=1'b1; 66 3'd1:begin rd_en<=1'b0;j<=j+1'b1;end 67 3'd2:begin Data_Out_r<=dout;j<=3'd0; end 68 endcase 69 assign Data_Out=Data_Out_r; 70 71 /****************************************************/ 72 73 74 75 76 endmodule
fifo_top:
1 module fifo_top( 2 clk,RSTn, 3 Data_Out 4 ); 5 input clk,RSTn; 6 output[3:0] Data_Out; 7 8 wire [3:0]din; 9 wire [3:0]dout; 10 wire wr_en,rd_en,full,empty; 11 12 13 /****************************************************/ 14 fifo_ip U0 ( 15 .clk(clk), // input clk 16 .rst(!RSTn), // input rst 17 .din(din), // input [3 : 0] din 18 .wr_en(wr_en), // input wr_en 19 .rd_en(rd_en), // input rd_en 20 .dout(dout), // output [3 : 0] dout 21 .full(full), // output full 22 .empty(empty) // output empty 23 ); 24 /*********************************************************/ 25 fifo_control U1 ( 26 .clk(clk), 27 .rst(!RSTn), 28 .Data_Out(Data_Out), 29 .din(din), 30 .wr_en(wr_en), 31 .full(full), 32 .dout(dout), 33 .rd_en(rd_en), 34 .empty(empty) 35 ); 36 37 38 endmodule
三、硬件部分
黑金SPARTAN开发板
1 NET "clk" LOC = T8; 2 NET "RSTn" LOC = L3; 3 4 NET "Data_Out[0]" LOC = P4; 5 NET "Data_Out[1]" LOC = N5; 6 NET "Data_Out[2]" LOC = P5; 7 NET "Data_Out[3]" LOC = M6;
