基于Verilog的按键检测实验
一、模块框图及基本思路
detect_module:检测按键输入脚的电平边沿变化
delay_10ms_module:延时消抖，输出按键有效信号
debounce_module:前两个模块的组合模块
key_control:按键信号控制Led
key_demo:顶层模块
二、软件部分
detect_module.v
1 module detect_module( 2 CLK,RSTn, 3 Key_Pin_In, 4 H2L_Sig,L2H_Sig 5 ); 6 input CLK,RSTn; 7 input Key_Pin_In; 8 output H2L_Sig,L2H_Sig; 9 10 /****************************************************/ 11 localparam T100us=50_000_000/1_000_000*100-1; 12 reg [15:0] Count_100us; 13 reg isEn; 14 15 always @(posedge CLK or negedge RSTn) 16 begin 17 if(!RSTn) 18 begin 19 Count_100us<=16'd0; 20 isEn<=1'b0; 21 end 22 else if(Count_100us==T100us) 23 isEn<=1'b1; 24 else Count_100us<=Count_100us+1'b1; 25 end 26 27 /****************************************************/ 28 reg H2L_Sig_r1,H2L_Sig_r2; 29 reg L2H_Sig_r1,L2H_Sig_r2; 30 always @(posedge CLK or negedge RSTn) 31 begin 32 if(!RSTn) 33 begin 34 H2L_Sig_r1<=1'b1; 35 H2L_Sig_r2<=1'b1; 36 L2H_Sig_r1<=1'b0; 37 L2H_Sig_r2<=1'b0; 38 end 39 else 40 begin 41 H2L_Sig_r1<=Key_Pin_In; 42 H2L_Sig_r2<=H2L_Sig_r1; 43 L2H_Sig_r1<=Key_Pin_In; 44 L2H_Sig_r2<=L2H_Sig_r1; 45 end 46 end 47 48 /****************************************************/ 49 50 assign H2L_Sig=isEn?(H2L_Sig_
delay_10ms_module.v
1 module delay10ms_module( 2 CLK,RSTn, 3 H2L_Sig,L2H_Sig, 4 Key_Sig_Out 5 ); 6 input CLK,RSTn; 7 input H2L_Sig,L2H_Sig; 8 output Key_Sig_Out; 9 10 /**********************************************/ 11 localparam T10ms=50_000_000/1000*10-1; 12 reg[31:0] Count_10ms; 13 reg isCount; 14 always @(posedge CLK or negedge RSTn) 15 begin 16 if(!RSTn) 17 begin 18 Count_10ms<=32'd0; 19 end 20 else if(Count_10ms==T10ms) Count_10ms<=32'd0; 21 else if(isCount) Count_10ms<=Count_10ms+1'b1; 22 end 23 24 /**********************************************/ 25 reg Key_Sig_Out_r; 26 reg [1:0]i; 27 always @(posedge CLK or negedge RSTn) 28 begin 29 if(!RSTn) 30 begin 31 Key_Sig_Out_r<=0; 32 i<=0; 33 isCount<=1'b0; 34 end 35 else 36 case(i) 37 2'd0:if(H2L_Sig) i<=2'd1; 38 else if(L2H_Sig) i<=2'd2; 39 2'd1:if(Count_10ms==T10ms) begin Key_Sig_Out_r<=1'b1;isCount<=1'b0;i<=2'd0;end 40 else isCount<=1'b1; 41 2'd2:if(Count_10ms==T10ms) begin Key_Sig_Out_r<=1'b0;isCount<=1'b0;i<=2'd0;end 42 else isCount<=1'b1; 43 44 endcase 45 end 46 /***************************************************/ 47 assign Key_Sig_Out=Key_Sig_Out_r; 48 49 endmodule
debounce_module.v
1 module debounce_module( 2 CLK,RSTn, 3 Key_Pin_In, 4 Key_Sig_Out 5 ); 6 input CLK,RSTn; 7 input Key_Pin_In; 8 output Key_Sig_Out; 9 10 wire H2L_Sig; 11 wire L2H_Sig; 12 13 detect_module U0( 14 .CLK(CLK), 15 .RSTn(RSTn), 16 .Key_Pin_In(Key_Pin_In), 17 .H2L_Sig(H2L_Sig), 18 .L2H_Sig(L2H_Sig) 19 ); 20 delay10ms_module U1( 21 .CLK(CLK), 22 .RSTn(RSTn), 23 .H2L_Sig(H2L_Sig), 24 .L2H_Sig(L2H_Sig), 25 .Key_Sig_Out(Key_Sig_Out) 26 ); 27 28 29 endmodule
key_control.v
1 module key_control( 2 CLK,RSTn, 3 Key_Sig, 4 Led 5 ); 6 input CLK,RSTn; 7 input Key_Sig; 8 output Led; 9 10 /***********************************/ 11 reg Key_Sig_r1,Key_Sig_r2; 12 wire Led_Sig; 13 always @(posedge CLK or negedge RSTn) 14 begin 15 if(!RSTn) 16 begin 17 Key_Sig_r1<=1'b0; 18 Key_Sig_r2<=1'b0; 19 end 20 else 21 begin 22 Key_Sig_r1<=Key_Sig; 23 Key_Sig_r2<=Key_Sig_r1; 24 end 25 end 26 assign Led_Sig=Key_Sig_r1&!Key_Sig_r2; 27 /************************************/ 28 reg rLed; 29 always @(posedge CLK or negedge RSTn ) 30 begin 31 if(!RSTn) rLed<=1'b0; 32 else if(Led_Sig) rLed<=~rLed; 33 end 34 assign Led=rLed; 35 endmodule
key_demo.v
1 module key_demo( 2 CLK,RSTn, 3 Key_Pin_In,Led 4 ); 5 input CLK,RSTn; 6 input [3:0]Key_Pin_In; 7 output [3:0]Led; 8 9 wire Key_Sig1; 10 key_control U0 ( 11 .CLK(CLK), 12 .RSTn(RSTn), 13 .Key_Sig(Key_Sig1), 14 .Led(Led[0]) 15 ); 16 debounce_module U1 ( 17 .CLK(CLK), 18 .RSTn(RSTn), 19 .Key_Pin_In(Key_Pin_In[0]), 20 .Key_Sig_Out(Key_Sig1) 21 ); 22 23 wire Key_Sig2; 24 key_control U2 ( 25 .CLK(CLK), 26 .RSTn(RSTn), 27 .Key_Sig(Key_Sig2), 28 .Led(Led[1]) 29 ); 30 debounce_module U3 ( 31 .CLK(CLK), 32 .RSTn(RSTn), 33 .Key_Pin_In(Key_Pin_In[1]), 34 .Key_Sig_Out(Key_Sig2) 35 ); 36 37 wire Key_Sig3; 38 key_control U4 ( 39 .CLK(CLK), 40 .RSTn(RSTn), 41 .Key_Sig(Key_Sig3), 42 .Led(Led[2]) 43 ); 44 debounce_module U5 ( 45 .CLK(CLK), 46 .RSTn(RSTn), 47 .Key_Pin_In(Key_Pin_In[2]), 48 .Key_Sig_Out(Key_Sig3) 49 ); 50 51 wire Key_Sig4; 52 key_control U6 ( 53 .CLK(CLK), 54 .RSTn(RSTn), 55 .Key_Sig(Key_Sig4), 56 .Led(Led[3]) 57 ); 58 debounce_module U7 ( 59 .CLK(CLK), 60 .RSTn(RSTn), 61 .Key_Pin_In(Key_Pin_In[3]), 62 .Key_Sig_Out(Key_Sig4) 63 ); 64 65 endmodule
三、硬件部分
黑金SPARTAN-6开发板
1 NET "CLK" LOC = T8; 2 NET "RSTn" LOC = L3; 3 4 NET "Led[0]" LOC = P4; 5 NET "Led[1]" LOC = N5; 6 NET "Led[2]" LOC = P5; 7 NET "Led[3]" LOC = M6; 8 9 NET "Key_Pin_In[0]" LOC = C3; 10 NET "Key_Pin_In[1]" LOC = D3; 11 NET "Key_Pin_In[2]" LOC = E4; 12 NET "Key_Pin_In[3]" LOC = E3;
