Chisel3 - 接口方向(Direction)
https://mp.weixin.qq.com/s/36jreQGpDLCCNfmUwI34lA
val io = IO(new Bundle { val in = Input(UInt(1.W)) val out = Output(UInt(1.W)) })
val io = IO(new Bundle { val isWr = Input(Bool()) val wrAddr = Input(UInt(8.W)) val wrData = Input(UInt(32.W)) val boot = Input(Bool()) val valid = Output(Bool()) val out = Output(UInt(32.W)) })
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