AD9850的FPGA实现--代码实现
下面结合代码对AD9850模块的调试进行分析
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首先是对AD9850上电复位的时序分析
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参数计算如下
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利用在状态机中的定时器,完成AD9850复位的状态转移
状态机中延时请参考这篇文章
http://www.cnblogs.com/whut-xxxy/archive/2011/05/21/2052652.html
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为了满足时序参数的要求，采用状态机来完成。
状态机图
1
2 // state_registers
3
4 reg [14:0] current_state;
5 reg [14:0] next_state;
6
7
8 always@(posedge clk or negedge reset_n)
9 if(!reset_n)
10 current_state <= IDLE;
11 else
12 current_state <= next_state;
13
14 // next_state logic
15
16 always@(*)
17 begin
18 /* 清定时器使能 开始 */
19 timer1_enable = 1'b0;
20 timer2_enable = 1'b0;
21 /* 清定时器使能 结束 */
22
23 case(current_state)
24
25 IDLE:
26 next_state = INIT_AD9850;
27 INIT_AD9850:
28 begin
29 timer1_enable = 1'b1;
30 if(timer1_done)
31 next_state = INIT_DONE;
32 else
33 next_state = INIT_AD9850;
34 en
35 INIT_DONE:
36 begin
37 timer2_enable = 1'b1;
38 if(timer2_done)
39 next_state = WR_COMMAND;
40 else
41 next_state = INIT_DONE;
42
43 end
44 WR_COMMAND:
45 next_state = WR_COMMAND_WAIT;
46 WR_COMMAND_WAIT:
47 next_state = WR_FREQ_1;
48 WR_FREQ_1:
49 next_state = WR_FREQ_1_WAIT;
50 WR_FREQ_1_WAIT:
51 next_state = WR_FREQ_2;
52 WR_FREQ_2:
53 next_state = WR_FREQ_2_WAIT;
54 WR_FREQ_2_WAIT:
55 next_state = WR_FREQ_3;
56 WR_FREQ_3:
57 next_state = WR_FREQ_3_WAIT;
58 WR_FREQ_3_WAIT:
59 next_state = WR_FREQ_4;
60 WR_FREQ_4:
61 next_state = WR_FREQ_4_WAIT;
62 WR_FREQ_4_WAIT:
63 next_state = FREQ_UPDATE;
64 FREQ_UPDATE:
65 next_state = FREQ_UPDATE_DONE;
66 FREQ_UPDATE_DONE:
67 next_state = FREQ_UPDATE_DONE;
68
69
70 endcase
71
72 end
73
74
75
76
77 always@(posedge clk or negedge reset_n)
78 if(!reset_n)
79 begin
80 {ad9850_w_clk_r,ad9850_fq_ud_r,ad9850_reset_r} <= 3'b000;
81 ad9850_data_r <= 8'h00;
82 end
83 else
84 case(next_state)
85
86 INIT_AD9850:
87 {ad9850_w_clk_r,ad9850_fq_ud_r,ad9850_reset_r} <= 3'b001;
88
89 INIT_DONE:
90 {ad9850_w_clk_r,ad9850_fq_ud_r,ad9850_reset_r} <= 3'b000;
91
92 WR_COMMAND:
93 ad9850_data_r <= 8'b0000_0000;
94
95 WR_COMMAND_WAIT:
96 ad9850_w_clk_r <= 1'b1;
97
98 WR_FREQ_1:
99 begin ad9850_data_r <= 8'h00; ad9850_w_clk_r <= 1'b0; end
100
101 WR_FREQ_1_WAIT:
102 ad9850_w_clk_r <= 1'b1;
103
104 WR_FREQ_2:
105 begin ad9850_data_r <= 8'h00; ad9850_w_clk_r <= 1'b0; end
106
107 WR_FREQ_2_WAIT:
108 ad9850_w_clk_r <= 1'b1;
109
110 WR_FREQ_3:
111 begin ad9850_data_r <= 8'h01; ad9850_w_clk_r <= 1'b0; end
112
113 WR_FREQ_3_WAIT:
114 ad9850_w_clk_r <= 1'b1;
115
116 WR_FREQ_4:
117 begin ad9850_data_r <= 8'had; ad9850_w_clk_r <= 1'b0; end
118
119 WR_FREQ_4_WAIT:
120 ad9850_w_clk_r <= 1'b1;
121
122 FREQ_UPDATE:
123 begin ad9850_w_clk_r <= 1'b0; ad9850_fq_ud_r <= 1'b1; end
124
125 FREQ_UPDATE_DONE:
126 ad9850_fq_ud_r <= 1'b1;
127 endcase
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需要注意的地方
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第一个控制字
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AD9850的AGND DGND AVDD DVDD如何接？
一般情况下。GND都接一起，VDD都接一起就可以。
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关于外部时钟源的选择
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关于AD9850的电源滤波
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原理图如下(未接入低通滤波器，由于是电流输出，因此接了一个50欧的负载电阻，产生压降)
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实测波形如下
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5HZ输出
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1khz输出
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2Mhz输出
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4.5Mhz输出
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50Mhz有源晶振作为时钟源，输出频率若再高，波形失真就比较严重了。。还有很多有待完善的地方。
