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将代码打包为一个IP模块 以FIFO代码为例：https://www.cnblogs.com/waqdgstd/p/15267726.html 1.打开向导 2.源文件和外围接口选择，这里不选AXI4 3.保存位置 4.最后检查后点解Package IP 将IP模块添加到库里面供搭建BD文件调用 B 阅读全文
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参考：https://www.cnblogs.com/aslmer/p/6114216.html 文章：Simulation and Synthesis Techniques for Asynchronous Asynchronous FIFO Design 异步FIFO的读写指针 写指针 写指针指 阅读全文
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// a 3-input look-up-table // In this question, you will design a circuit for an 8x1 memory, // where writing to the memory is accomplished by shiftin 阅读全文
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## 题目要求 使用verilog描述如图所示得移位寄存器： Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copie 阅读全文
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//四级移位寄存器 module top_module ( input clk, input resetn, // synchronous reset input in, output reg out); reg [2:0] Q; always @(posedge clk)begin if(~res 阅读全文
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//Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1. 草图 verilog描述 module top_module( input clk, input reset, // Active-high synch 阅读全文
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1.描述电路图里面的一个子模块 Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a fli 阅读全文
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Build this LFSR. The reset should reset the LFSR to 1 module top_module( input clk, input reset, // Active-high synchronous reset to 5'h1 output reg [ 阅读全文
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// Build a 64-bit arithmetic shift register, // with synchronous load. The shifter can shift both left and right, // and by 1 or 8 bit positions, sele 阅读全文
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verilog代码： // Build a 100-bit left/right rotator, with synchronous load and left/right enable. //A rotator shifts-in the shifted-out bit from the othe 阅读全文