Nios II对flash进行读写(DE2)
Abstract
在DE2板子上,除了8MB的SDRAM,排名最大的就是4MB的Flash了,本文讨论在Nios II上对flash进行读写。
Introduction
使用环境:Quartus II9.1 + Nios II IDE 9.1
SOPC Builder部分
step 1:要使用Flash首先需要添加三态桥(Tristate Bridge)
Note :在设置SDRAM时要注意各个参数ADDER为12bits,DATA为16位。在设置Flash时要设置ADDER22bits,, DATA为8bits。
Step 2: 对flash的参数设置
地址和数据位的设置
Timing设置
Top Module部分
Flash_test.v / verilog
/* (C)Wang Yabin & Gao Xiaomei 2016 http://home.cnblogs.com/u/wangyabin121/ Filename : flash_tes.v Compiler : Quartus II 9.1 + Nos II IDE9.1 Description : DE2_NIOS lite version 1.2 Release : 07/07/2016 1.0 */ module flash_test( input CLOCK_50, // On Board 50 MHz input [3:0] KEY, // Pushbutton[3:0] inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits output [11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits output DRAM_LDQM, // SDRAM Low-byte Data Mask output DRAM_UDQM, // SDRAM High-byte Data Mask output DRAM_WE_N, // SDRAM Write Enable output DRAM_CAS_N, // SDRAM Column Address Strobe output DRAM_RAS_N, // SDRAM Row Address Strobe output DRAM_CS_N, // SDRAM Chip Select output DRAM_BA_0, // SDRAM Bank Address 0 output DRAM_BA_1, // SDRAM Bank Address 0 output DRAM_CLK, // SDRAM Clock output DRAM_CKE, // SDRAM Clock Enable inout [7:0] FL_DQ, // FLASH Data bus 8 Bits output [21:0] FL_ADDR, // FLASH Address bus 22 Bits output FL_WE_N, // FLASH Write Enable output FL_RST_N, // FLASH Reset output FL_OE_N, // FLASH Output Enable output FL_CE_N // FLASH Chip Enable ); wire CPU_CLK; wire CPU_RESET; // Flash assign FL_RST_N = 1'b1; Reset_Delay u0 ( .iRST(KEY[0]), .iCLK(CLOCK_50), .oRESET(CPU_RESET) ); SDRAM_PLL u1 ( .inclk0(CLOCK_50), .c0(DRAM_CLK), .c1(CPU_CLK) ); nios_ii u2( .clk (CPU_CLK), .clk_50 (CLOCK_50), .data_to_and_from_the_cfi_flash_0 (FL_DQ), .read_n_to_the_cfi_flash_0 (FL_OE_N), .reset_n (CPU_RESET), .select_n_to_the_cfi_flash_0 (FL_CE_N), .write_n_to_the_cfi_flash_0 (FL_WE_N), .zs_addr_from_the_sdram_0 (DRAM_ADDR), .zs_ba_from_the_sdram_0 ({DRAM_BA_1,DRAM_BA_0}), .zs_cas_n_from_the_sdram_0 (DRAM_CAS_N), .zs_cke_from_the_sdram_0 (DRAM_CKE), .zs_cs_n_from_the_sdram_0 (DRAM_CS_N), .zs_dq_to_and_from_the_sdram_0 (DRAM_DQ), .zs_dqm_from_the_sdram_0 ({DRAM_UDQM,DRAM_LDQM}), .zs_ras_n_from_the_sdram_0 (DRAM_RAS_N), .zs_we_n_from_the_sdram_0 (DRAM_WE_N) ); endmodule
在Nios II用HAL对Flash做读写
hello_word.c /c
#include <stdio.h> #include "system.h" // CFI_FLASH_NAME #include "sys/alt_flash.h" // flash HAL int main() { alt_flash_fd *fd; int i, j, return_code; i = 10; j = 9; // open flash fd = alt_flash_open_dev(CFI_FLASH_0_NAME); if (!fd) { printf("alt_flash_open_dev error\n"); return -1; } // write flash return_code = alt_write_flash(fd, 0, &i, sizeof(int)); if (return_code) { printf("alt_write_flash error\n"); return -1; } // read flash return_code = alt_read_flash(fd, 0, &j, sizeof(int)); if (return_code) { printf("alt_read_flash error\n"); return -1; } // compare input & output if (i == j) printf("i=%d, j=%d, flash read / write OK\n", i, j); else printf("i=%d, j=%d, flash read / write error\n", i, j); // close flash alt_flash_close_dev(fd); return 0; }
实验结果
Conclusion
事实上Altera还提供了其他对flash存取的HAL,以Quartus II 9.1而言,位于C:\altera\91\nios2eds\components\altera_hal\HAL\inc\sys\alt_flash.h,可以自行参考。
DE2-70与DE2类似,就不另外讨论,只有SOPC Builder的Flash paramters & timing不太一样。
2016-07-07
20:00:34
参考文章
http://www.cnblogs.com/kingst/archive/2010/05/25/1743837.html