小梅哥课程学习——数码管动态扫描显示的verilog实现(C)

//动态数码管扫描，通过这种方式可以节约引脚
//可以使用三八译码器来切换数码管位
//要求每个数码管每20ms都要点亮一次，20/8=2.5ms
//源代码1用的是组合逻辑
module hex8(
    clk,
    reset_n,
    disp_data,
    sel,
    seg
    );
    input clk;
    input reset_n;
    input [31:0] disp_data;
    output reg [7:0] sel;
    output reg [7:0] seg;
    

    reg clk_1k;
    reg [14:0]div_cnt;
    //设置分频计数时钟
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        div_cnt <= 0;
    else if(div_cnt >= 24999)
        div_cnt <= 0;
    else
        div_cnt <= div_cnt + 1'b1;
        //定义1ms的时钟（1khz）
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        clk_1k <= 0;
    else if(div_cnt >= 24999)
        clk_1k <= !clk_1k;
    //这种门时钟在绝大多数不推荐使用
    reg [2:0] num_cnt;
    always@(posedge clk_1k or negedge reset_n)
    if(!reset_n)
        num_cnt <= 0;
    else
        num_cnt <= num_cnt + 1'b1; 
    
    //书写3—8译码器
    always@(*)begin
        case(num_cnt)
            0:sel <= 8'b0000_0001;
            1:sel <= 8'b0000_0010;
            2:sel <= 8'b0000_0100;
            3:sel <= 8'b0000_1000;
            4:sel <= 8'b0001_0000;
            5:sel <= 8'b0010_0000;
            6:sel <= 8'b0100_0000;
            7:sel <= 8'b1000_0000;
        endcase
    end
   
   reg [3:0] dis_tmp;
   always@(*)begin
        case(num_cnt)
            7:dis_tmp <= disp_data[31:28];
            6:dis_tmp <= disp_data[27:24];
            5:dis_tmp <= disp_data[23:20];
            4:dis_tmp <= disp_data[19:16];
            3:dis_tmp <= disp_data[15:12];
            2:dis_tmp <= disp_data[11:8];
            1:dis_tmp <= disp_data[7:4];
            0:dis_tmp <= disp_data[3:0];
        endcase
    end
    
    always@(*)begin
        case(dis_tmp)
            0:seg <= 8'hc0;
            1:seg <= 8'hf9;
            2:seg <= 8'ha4;
            3:seg <= 8'hb0;
            4:seg <= 8'h99;
            5:seg <= 8'h92;
            6:seg <= 8'h82;
            7:seg <= 8'hf8;
            8:seg <= 8'h80;
            9:seg <= 8'h90;
            4'ha:seg <= 8'h88;
            4'hb:seg <= 8'h83;
            4'hc:seg <= 8'hc6;
            4'hd:seg <= 8'ha1;
            4'he:seg <= 8'h86;
            4'hf:seg <= 8'h8e;
        endcase
    end
endmodule

//源代码2用的是时序逻辑
module hex8_2(
    clk,
    reset_n,
    disp_data,
    sel,
    seg
    );
    input clk;
    input reset_n;
    input [31:0] disp_data;
    output reg [7:0] sel;
    output reg [7:0] seg;
    

    reg clk_1k;
    reg [14:0]div_cnt;
    //设置分频计数时钟
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        div_cnt <= 0;
    else if(div_cnt >= 49999)
        div_cnt <= 0;
    else
        div_cnt <= div_cnt + 1'b1;
        //这种门控时钟在绝大多数场合不允许使用
        //定义1ms的时钟（1khz）
//    always@(posedge clk or negedge reset_n)
//    if(!reset_n)
//        clk_1k <= 0;
//    else if(div_cnt >= 24999)
//        clk_1k <= !clk_1k;
    
    //使能时钟
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        clk_1k <= 0;
    else if(div_cnt >= 49999)
        clk_1k <= 1;
    else
        clk_1k <= 0;
        
    reg [2:0] num_cnt;
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        num_cnt <= 0;
    else if(clk_1k)//这里面使用的就是使能时钟
        num_cnt <= num_cnt + 1'b1; 
    
    //书写3—8译码器
    always@(posedge clk)begin//将组合逻辑用时序的时钟，结果更加精确。
        case(num_cnt)
            0:sel <= 8'b0000_0001;
            1:sel <= 8'b0000_0010;
            2:sel <= 8'b0000_0100;
            3:sel <= 8'b0000_1000;
            4:sel <= 8'b0001_0000;
            5:sel <= 8'b0010_0000;
            6:sel <= 8'b0100_0000;
            7:sel <= 8'b1000_0000;
        endcase
    end
   
   reg [3:0] dis_tmp;
   always@(posedge clk)begin
        case(num_cnt)
            7:dis_tmp <= disp_data[31:28];
            6:dis_tmp <= disp_data[27:24];
            5:dis_tmp <= disp_data[23:20];
            4:dis_tmp <= disp_data[19:16];
            3:dis_tmp <= disp_data[15:12];
            2:dis_tmp <= disp_data[11:8];
            1:dis_tmp <= disp_data[7:4];
            0:dis_tmp <= disp_data[3:0];
        endcase
    end
    
    always@(posedge clk)begin
        case(dis_tmp)
            0:seg <= 8'hc0;
            1:seg <= 8'hf9;
            2:seg <= 8'ha4;
            3:seg <= 8'hb0;
            4:seg <= 8'h99;
            5:seg <= 8'h92;
            6:seg <= 8'h82;
            7:seg <= 8'hf8;
            8:seg <= 8'h80;
            9:seg <= 8'h90;
            4'ha:seg <= 8'h88;
            4'hb:seg <= 8'h83;
            4'hc:seg <= 8'hc6;
            4'hd:seg <= 8'ha1;
            4'he:seg <= 8'h86;
            4'hf:seg <= 8'h8e;
        endcase
    end
endmodule



//仿真文件
`timescale 1ns / 1ps
module hex8_tb();
    reg clk;
    reg reset_n;
    reg [31:0] disp_data;
    wire [7:0] sel;
    wire [7:0] seg;
    hex8 hex8_inst0(
    clk,
    reset_n,
    disp_data,
    sel,
    seg
    );
    initial clk = 1;
    always #10 clk = !clk;
    
    initial begin
        reset_n = 0;
        disp_data = 32'h00000000;
        #201;
        reset_n = 1;
        #2000;
        disp_data = 32'h12345678;
        #10000000;
        disp_data = 32'h9abcdef0;
        #10000000;
        $stop;
    
    end
endmodule

//板级实验所用的测试文件，只有AX735才能班级实验，这个是扩展板

module hex8_test(
    clk,
    reset_n,
    sel,
    seg
    );
    input clk;
    input reset_n;
    output [7:0] sel;
    output [7:0] seg;
    
    wire [31:0] disp_data;
    
    hex8_2 hex8_2_inst0(
    clk,
    reset_n,
    disp_data,
    sel,
    seg
    );
    assign disp_data = 32'h13579bdf;
    
endmodule

使用门控时钟，将门控时钟直接作为DFF的工作时钟，没有ENA的情况下忽略ENA

使用使能时钟的情况，DFF的工作时钟继续使用全局的高质量时钟，而将使能时钟作为DFF的使能信号使用。

2023-03-28 21:10:13