中值滤波消除椒盐噪声，高斯滤波消除高斯噪声

  1 `timescale 1ns / 1ps
  2 //////////////////////////////////////////////////////////////////////////////////
  3 // Company: 
  4 // Engineer: 
  5 // 
  6 // Create Date: 2019/03/07 10:06:43
  7 // Design Name: 
  8 // Module Name: matrix
  9 // Project Name: 
 10 // Target Devices: 
 11 // Tool Versions: 
 12 // Description: 
 13 // 
 14 // Dependencies: 
 15 // 
 16 // Revision:
 17 // Revision 0.01 - File Created
 18 // Additional Comments:
 19 // 
 20 //////////////////////////////////////////////////////////////////////////////////
 21 
 22 
 23 module matrix #(    
 24     parameter COL = 640    ,
 25     parameter ROW = 480    
 26 )
 27 (
 28     input                 clk            ,
 29     input                 rst_n        ,
 30     
 31     input               data_de        ,
 32     input         [7:0]     data        ,
 33     
 34     output                   matrix_de    ,
 35 
 36     output reg [7:0]    matrix11    ,
 37     output reg [7:0]    matrix12    ,
 38     output reg [7:0]    matrix13    ,
 39     
 40     output reg [7:0]    matrix21    ,
 41     output reg [7:0]    matrix22    ,
 42     output reg [7:0]    matrix23    ,
 43     
 44     output reg [7:0]    matrix31    ,
 45     output reg [7:0]    matrix32    ,
 46     output reg [7:0]    matrix33    
 47 );
 48 
 49 wire     [7:0]      row3_data    ;                                                                                                           
 50 wire     [7:0]      row2_data    ;
 51 wire     [7:0]      row1_data    ;
 52 
 53 reg      [15:0]    col_cnt        ;
 54 reg      [15:0]    row_cnt        ;
 55 
 56 wire            row2_rd        ;
 57 
 58 reg             data_de_r    ;
 59 reg             data_de_r1    ;
 60 
 61 wire            u1_empty    ;    
 62 wire            u2_empty    ;
 63 
 64 wire            wr_en        ;
 65 
 66 always@(posedge clk)
 67     if(!rst_n)    
 68         col_cnt <= 'd0;
 69     else if(col_cnt==COL-1)
 70         col_cnt <= 'd0;
 71     else if(data_de==1'b1)
 72         col_cnt <= col_cnt + 1'b1;
 73     else
 74         col_cnt <= col_cnt;
 75 
 76 always@(posedge clk)
 77     if(!rst_n)    
 78         row_cnt <= 'd0;
 79     else if(col_cnt==COL-1&&row_cnt==ROW-1)
 80         row_cnt <= 'd0;
 81     else if(col_cnt==COL-1)
 82         row_cnt <= row_cnt + 1'b1;
 83     else
 84         row_cnt <= row_cnt;
 85 
 86 always@(posedge clk)
 87     if(!rst_n)    
 88         data_de_r <= 1'b0;
 89     else
 90         data_de_r <= data_de;
 91 
 92 always@(posedge clk)
 93     if(!rst_n)    
 94         data_de_r1 <= 1'b0;
 95     else
 96         data_de_r1 <= data_de_r;
 97         
 98 assign  matrix_de = data_de_r1    ;    
 99 assign     row3_data = data;
100 assign  wr_en = data_de&&row_cnt<ROW-1;
101 
102 fifo_matrix_buf u1_fifo_matrix_buf (
103   .rst            (~rst_n            ),
104   .wr_clk        (clk            ), 
105   .rd_clk        (clk            ), 
106   .din            (row3_data        ),    
107   .wr_en        (wr_en            ),  
108   .rd_en        (row2_rd        ),  
109   .dout            (row2_data        ),   
110   .full            (                ),   
111   .empty        (u1_empty        )       
112 );
113 
114 fifo_matrix_buf u2_fifo_matrix_buf (
115   .rst            (~rst_n            ),
116   .wr_clk        (clk            ), 
117   .rd_clk        (clk            ), 
118   .din            (row2_data        ),    
119   .wr_en        (wr_en            ),  
120   .rd_en        (row2_rd        ),  
121   .dout            (row1_data        ),   
122   .full            (                ),   
123   .empty        (u2_empty        )       
124 );
125 
126 assign row2_rd = data_de&&row_cnt>0;
127 
128 always@(posedge clk)
129     if(!rst_n)
130         begin
131             {matrix11, matrix12, matrix13} <= 24'd0;
132             {matrix21, matrix22, matrix23} <= 24'd0;
133             {matrix31, matrix32, matrix33} <= 24'd0;
134         end
135     else if(data_de==1'b1)
136         begin
137             {matrix11, matrix12, matrix13} <= {matrix12, matrix13, row1_data};
138             {matrix21, matrix22, matrix23} <= {matrix22, matrix23, row2_data};
139             {matrix31, matrix32, matrix33} <= {matrix32, matrix33, row3_data};
140         end
141     else
142         begin
143             {matrix11, matrix12, matrix13} <= 24'd0;
144             {matrix21, matrix22, matrix23} <= 24'd0;
145             {matrix31, matrix32, matrix33} <= 24'd0;
146         end        
147 
148 
149 
150 
151 
152         
153     
154 
155 endmodule

 

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/01/13 23:18:52
// Design Name: 
// Module Name: ave_filter
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module ave_filter #(
    parameter COL=640,
    parameter ROW=480
) 
(
    input                 clk            ,
    input                 rst_n        ,
    input               y_vs        ,
    input               y_de        ,
    input  [7:0]         y_data        ,
    output              ave_vs        ,
    output              ave_de        ,
    output [7:0]        ave_data   
);

wire            matrix_de     ;

wire   [7:0]    matrix11     ;
wire   [7:0]    matrix12     ;
wire   [7:0]    matrix13     ;

wire   [7:0]    matrix21     ;
wire   [7:0]    matrix22     ;
wire   [7:0]    matrix23     ;

wire   [7:0]    matrix31     ;
wire   [7:0]    matrix32     ;
wire   [7:0]    matrix33     ;

reg    [3:0]    matrix_de_r  ;

reg    [15:0]   one_line     ;
reg    [15:0]   second_line  ;
reg    [15:0]   third_line   ;

reg    [15:0]   add_line     ;

reg             pre_ave_de    ;
reg    [31:0]   pre_ave_data0 ;
wire   [7:0]    pre_ave_data  ;



matrix    #(
    .COL(COL),
    .ROW(ROW)
)
u1_matrix
(
    .clk        (clk        ),
    .rst_n        (rst_n        ),
    .data_de    (y_de        ),
    .data        (y_data        ),
    
    .matrix_de    (matrix_de    ),
    .matrix11    (matrix11    ),
    .matrix12   (matrix12    ),
    .matrix13   (matrix13    ),
    .matrix21   (matrix21    ),
    .matrix22   (matrix22    ),
    .matrix23   (matrix23    ),
    .matrix31   (matrix31    ),
    .matrix32   (matrix32    ),
    .matrix33   (matrix33    )
);

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        matrix_de_r     <=  4'd0;
    else
        matrix_de_r     <=  {matrix_de_r[2:0],matrix_de};
        
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        one_line <= 'd0;
    else if(matrix_de==1'b1)
        one_line <= matrix11+matrix12+matrix13;
    else    
        one_line <= 'd0;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        second_line <= 'd0;
    else if(matrix_de==1'b1)
        second_line <= matrix21+matrix22+matrix23;
    else    
        second_line <='d0;                

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        third_line <= 'd0;
    else if(matrix_de==1'b1)
        third_line <= matrix31+matrix32+matrix33;
    else    
        third_line <='d0;
        
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        add_line <= 'd0;
    else if(matrix_de_r[0]==1'b1)
        add_line <= one_line+second_line+third_line;
    else    
        add_line <= 'd0;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        pre_ave_de <= 1'b0;
    else if(matrix_de_r[1]==1'b1)
        pre_ave_de <= 1'b1;
    else
        pre_ave_de <= 1'b0;
        
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        pre_ave_data0 <= 'd0;
    else  if(matrix_de_r[1]==1'b1)
        pre_ave_data0 <= add_line*7282;
    else
        pre_ave_data0 <= 'd0;    
    
assign pre_ave_data = pre_ave_data0[23:16];
    
move_cnter    #(
    .COL(COL),
    .ROW(ROW),
    .DW (8  )
)
u1_move_cnter(
    .clk            (clk               ),
    .rst_n          (rst_n             ),
    .i_de             (pre_ave_de      ),
    .i_data            (pre_ave_data    ),
    .o_de           (ave_de            ),
    .o_data            (ave_data       )
);        

assign ave_vs = y_vs;

endmodule

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/03/29 23:06:51
// Design Name: 
// Module Name: move_cnter
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module move_cnter #(
    parameter COL=640,
    parameter ROW=480,
    parameter DW =24

)
(
    input                         clk            ,
    input                         rst_n          ,    
    input                         i_de         ,
    input          [DW-1:0]        i_data        ,
    
    output reg                    o_de           ,
    output reg    [DW-1:0]        o_data    
);

reg  [15:0]     col_cnt            ;
reg  [15:0]     row_cnt            ;
    
reg  [15:0]     hcnt            ;
reg  [15:0]     vcnt            ;

reg             cnt_de          ;
reg  [7:0]      cnt             ;
reg             o_de_r           ;
    
reg             o_de_r1         ;
reg  [DW-1:0]    o_data_r           ;

reg  [15:0]     data_cnt        ;

wire              o_de_r2          ;  
wire [DW-1:0]      o_data_r2        ;


always@(posedge clk or negedge rst_n)
    if(!rst_n)
        col_cnt <= 'd0;
    else if(col_cnt==COL-1)
        col_cnt <= 'd0;
    else if(i_de==1'b1)
        col_cnt <= col_cnt + 1'b1;
    else
        col_cnt <= col_cnt;
        
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        row_cnt <= 'd0;
    else if(col_cnt==COL-1&&row_cnt==ROW-1)
        row_cnt <= 'd0;
    else if(col_cnt==COL-1)
        row_cnt <= row_cnt + 1'b1;
    else
        row_cnt <= row_cnt;
//去除第一行数据
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        o_de_r1  <= 1'b0;
    else if(row_cnt>=1&&row_cnt<=ROW-1&&i_de)
        o_de_r1  <= 1'b1;
    else
        o_de_r1  <= 1'b0;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        o_data_r  <= 'd0;
    else if(row_cnt>=1&&row_cnt<=ROW-1&&i_de)
        o_data_r  <= i_data;
    else
        o_data_r  <= 'd0;

//一帧数据计数完            
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        cnt_de <= 1'b0;
    else if(cnt=='d99)  //实际波形为160个周期
        cnt_de <= 1'b0;
    else if(col_cnt==COL-1&&row_cnt==ROW-1)
        cnt_de <= 1'b1;
    else
        cnt_de <= cnt_de;            
                
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        cnt <= 'd0;
    else if(cnt=='d99)
        cnt <= 'd0;
    else if(cnt_de==1'b1)
        cnt <= cnt + 1'b1;
    else
        cnt <= cnt;        
        
always@(posedge clk or negedge rst_n) //最后一行数据补零的标志位
    if(!rst_n)
        o_de_r <= 1'b0;        
    else if(data_cnt==COL-1)
        o_de_r <= 1'b0;
    else if(cnt=='d99)
        o_de_r <= 1'b1;
    else
        o_de_r <= o_de_r;    

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        data_cnt <='d0;        
    else if(data_cnt==COL-1)
        data_cnt <= 'd0;
    else if(o_de_r==1'b1)
        data_cnt <= data_cnt + 1'b1;
    else
        data_cnt <= data_cnt;    

assign o_de_r2     =       o_de_r||o_de_r1;    
assign o_data_r2   =    o_de_r1?o_data_r:'d0; 

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        hcnt <= 'd0;
    else if(hcnt==COL-1)
        hcnt <= 'd0;
    else if(o_de_r2==1'b1)
        hcnt <= hcnt + 1'b1;
    else
        hcnt <= hcnt;
        
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        vcnt <= 'd0;
    else if(hcnt==COL-1&&vcnt==ROW-1)
        vcnt <= 'd0;
    else if(hcnt==COL-1)
        vcnt <= vcnt + 1'b1;
    else
        vcnt <= vcnt;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        o_de <= 1'b0;
    else
        o_de <= o_de_r2; 
//去掉了第一列的数据
always@(posedge clk or negedge rst_n)
    if(!rst_n)
        o_data <= 'd0;
    else if(hcnt>0&&hcnt<COL-1&&vcnt>0&&vcnt<ROW-1)
        o_data <= o_data_r2;
    else
        o_data <= 'd0;
        
        
        
            
endmodule