采用流水线结构的CIC 抽取滤波器结构如下:// 三级CIC抽取器实例:cic3_decimator.Vmodule cic3_decimator(clk, x_in, y_out); parameter STATE_HOLD = 1'b0, STATE_SAMPLE = 1'b1; input clk; // 输入时钟 input [7:0] x_in; // 输入8位数据 output [25:0] y_out; // 输出26位数据 reg state, derived_clk; reg [4:0] cou... Read More
posted @ 2014-02-04 00:01 乐富道 Views(4223) Comments(0) Diggs(0) Edit
cordic 算法知道正弦和余弦值,求反正切,即角度。采用用不断的旋转求出对应的正弦余弦值,是一种近似求解发。旋转的角度很讲求,每次旋转的角度必须使得 正切值近似等于 1/(2^N)。旋转的目的是让Y轴趋近与0。把每次旋转的角度累加,即得到旋转的角度和即为正切值。比如Y轴旋转45度,则值减小1/2;... Read More
posted @ 2014-01-28 23:05 乐富道 Views(40967) Comments(0) Diggs(6) Edit
本文主要分析MII/RMII/SMII,以及GMII/RGMII/SGMII接口的信号定义,及相关知识,同时本文也对RJ-45接口进行了总结,分析了在10/100模式下和1000M模式下的设计方法。MII接口提供了MAC与PHY之间、PHY与STA(Station Management)之间的互联技... Read More
posted @ 2014-01-28 12:44 乐富道 Views(80029) Comments(0) Diggs(2) Edit
总结下常见的对串行数据采样的三种方式:1. 全采样存储方式:采用过采样,用过采样时钟,用移位寄存器移位,把每次采样值都存起来。采用高速的过采样时钟运行。然后等待触发条件,(就是找到数据的起始点条件,触发),然后从所有的记录到寄存器的采样值中,按照某种对应的关系选取。起始采样点必须做合适的触发。这样需要很长的寄存器串起来。对于数据太长,实现起来有限制。另外就是,满足触发条件就抽取一次过采样出来的寄存器值,触发条件很重要。2. 计数器作为触发方式:采用过采样,用过采样时钟,丢数据的起始点采用触发方式,数据到了,就启动计数器,这个计数器的值正好为过采样时钟的倍数;然后存数据的时候,选择计数器的某个值 Read More
posted @ 2014-01-26 10:30 乐富道 Views(1304) Comments(0) Diggs(0) Edit
http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-2Data Link Layer PacketsAside from wrapping TLPs with its header (2 bytes) and adding a CRC at the end (LCRC actually, 4 bytes), the Data Link layer runs packets of its own for maintaining reliable transmission. These special p Read More
posted @ 2014-01-14 16:35 乐富道 Views(559) Comments(0) Diggs(0) Edit
http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1Down to the TLP: How PCI express devices talk (Part I)ForewordWhile I was writing the Xillybus IP core for PCI express, I quickly found out that it’s very difficult to start off: Online resources as well as the official spec b Read More
posted @ 2014-01-14 16:33 乐富道 Views(778) Comments(0) Diggs(0) Edit
verilog中的有符号数运算http://hi.baidu.com/lixu1113/item/d00dc095f86aed48f142159averilog中的有符号数运算有符号数的计算:若有需要关于有号数的计算,应当利用Verilog 2001所提供的signed及$signed()机制。Ex:inputsigned [7:0] a, b;outputsigned [15:0] o;assign o = a * b;orinput[7:0] a, b;output [15:0] o;wire signed [15:0] o_sgn;assisn o_sgn = $signed(a) * Read More
posted @ 2014-01-05 12:28 乐富道 Views(1810) Comments(0) Diggs(0) Edit
Signed comparison in Verilog¶When you write this in Verilog:wire [7:0] a;wire [7:0] b;wire less;assign less = (a < b);the comparison between a and b is unsigned, that is a and b are numbers in the range 0-255. Writing this instead:wire [7:0] a;wire [7:0] b;wire less;assign less = ($signed(a) Read More
posted @ 2014-01-05 12:16 乐富道 Views(2026) Comments(0) Diggs(0) Edit
http://baike.baidu.com/view/398.htm拓扑学上的欧拉公式欧拉公式是指以欧拉命名的诸多公式。其中最著名的有,复变函数中的欧拉幅角公式--将复数、指数函数与三角函数联系起来; 拓扑学中的欧拉多面体公式;初等数论中的欧拉函数公式。 此外还包括其他一些欧拉公式,比如分式公式等... Read More
posted @ 2013-02-22 16:30 乐富道 Views(5752) Comments(0) Diggs(0) Edit
http://blog.csdn.net/erizen/article/details/58635501、符号能量问题 请问各位大虾,像4QAM,16QAM,32QAM,64QAM调制每符号平均能量怎么求解?我看别人程序时,16QAM得每符号平均能为10,不知道怎么求出来的。我想知道对于这些调制方式,怎么加噪的,我看一段程序如下: Eav=10*d^2; % energy per symbol snr=10^(SNRindB(p)/10); % SNR per bit (given) sgma=sqrt(Eav/(8*snr)); % noise variance它是16QAM调制算噪声均方差 Read More
posted @ 2013-02-15 20:37 乐富道 Views(6223) Comments(0) Diggs(1) Edit