verilog中的有符号数运算http://hi.baidu.com/lixu1113/item/d00dc095f86aed48f142159averilog中的有符号数运算有符号数的计算：若有需要关于有号数的计算，应当利用Verilog 2001所提供的signed及$signed()机制。Ex:inputsigned [7:0] a, b;outputsigned [15:0] o;assign o = a * b;orinput[7:0] a, b;output [15:0] o;wire signed [15:0] o_sgn;assisn o_sgn = $signed(a) * Read More
Signed comparison in Verilog¶When you write this in Verilog:wire [7:0] a;wire [7:0] b;wire less;assign less = (a < b);the comparison between a and b is unsigned, that is a and b are numbers in the range 0-255. Writing this instead:wire [7:0] a;wire [7:0] b;wire less;assign less = ($signed(a) Read More